Thermal management of power electronics modules packaged by a stacked-plate technique

The research presented in this paper is part of a multidisciplinary research program of the Center for Power Electronics Systems at Virginia Tech. The program supported by the Office of Naval Research focuses on the development of innovative technologies for packaging power electronics building blocks. The primary objective of this research is to improve package performance and reliability through thermal management, i.e., reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thermal modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.     

Evaluation and optimization of package processing and design through solder joint profile prediction

Solder joints are generated using a variety of methods to provide both mechanical and electrical connection for applications such as flip-chip, wafer level packaging, fine pitch, ball-grid array, and chip scale packages. Solder joint shape prediction has been incorporated as a key tool to aid in process development, wafer level and package level design and development, assembly, and reliability enhancement. This work demonstrates the application of an analytical model and the Surface Evolver software in analyzing a variety of solder processing methods and package types. Bump and joint shape prediction was conducted for the design of wafer level bumping, flip-chip assembly, and wafer level packaging. The results from the prediction methodologies are validated with experimentally measured geometries at each level of design.     

Low-cost, multi-GHz electrical packaging for serial optoelectroniclinks utilizing vertical cavity surface emitting lasers

Recent advances in semiconductor laser technology, specifically the emergence of vertical cavity surface emitting lasers (VCSELs), have created room for substantial improvements in the performance of low-cost, fiber-optic links. However, traditional electronic packaging of the VCSELs and detectors severely limits the performance of these new devices. In two previous papers from this laboratory [1996, 1997], traditional laser packages were described, modeled, measured and evaluated. Further, a new improved conceptual package, referred to as the optical package for advanced lasers (OPAL), was presented, as were a set of design guidelines for a new generation of packages for VCSELs and detectors. This paper, describing a continuation of the previous work, discusses the design, modeling, fabrication, and demonstration of OPALs in a laboratory environment. Measured results recorded from VCSELs packaged in OPALs operating to 5 Gbit/s data rates are presented     

应用于三维封装中的硅通孔技术

随着集成电路日新月异的发展,当半导体器件工艺进展到纳米级别后,传统的二维领域封装已渐渐不能满足电路高性能、低功耗与高可靠性的要求。为解决这一问题,三维封装成为了未来封装发展的主流。文章简要介绍了三维封装的工艺流程,并重点介绍了硅通孔技术的现阶段在CSP领域的应用,以及其未来的发展方向。     

High-power robust semiconductor electronics technologies in the new millennium

This paper presents an overview of power semiconductor devices for the development of advanced robust high-performance power electronic systems for the new millennium. Material and device technologies on silicon and wide energy band-gap semiconductors are discussed along with switching circuits and topologies. Short-term and long-term reliability issues of power semiconductor devices are discussed. An approach is presented to correlate converter field failures to dynamic switching stresses, residual defects and contaminants left in the semiconductor power switch, packaging, and thermal management. Component and system level simulation, modeling and CAD requirements are evaluated. System-level optimization is proposed as an essential requirement to develop robust power systems at affordable cost.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Materials,process science & technology at Sandia's center for compound semiconductor technology: CCST

The CCST embodies a wide range of capabilities for advancing the stae of the art in compound semiconductor device development. The next generation of devices will depend critically on advances in materials and materials processing, and the CCST has been at the forefront in developing both the new materials and the necessary processing techniques to realize exciting new device concepts. In these efforts, Sandia's CCST is interested in increasingly teaming with the private sector to accelarate the conjunction between research and development and near-term industry applications. Numerous companies are already engaged in collaborative efforts with Sandia; these include     

复合型微通道热沉设计与制作技术研究

从大功率半导体激光器可靠性封装和应用考虑,利用商用有限元软件Abaqus与CFdesign对微通道热沉材料、结构进行优化设计,结合相应的制造工艺流程制备实用化复合型微通道热沉。微通道热沉尺寸为27 mm×10.8 mm×1.5 mm,并利用大功率半导体激光阵列器件对所制备热沉进行散热能力、封装产生的"微笑效应"进行了测试,复合微通道热沉热阻约0.3 K/W,"微笑"值远小于无氧铜微通道封装线阵列,可以控制在1μm以下。复合型微通道热沉能满足半导体激光阵列器件高功率集成输出的散热需求与硬焊料封装的可靠性要求。     

国内大功率半导体激光器研究及应用现状

近年来,国内外在大功率半导体激光器方面的研究均取得了很大的进展。其中,大功率半导体激光器列阵的研究和应用成为最大的亮点,如超高电光转换效率、高亮度和高可靠性等主要光电特性均实现了巨大的突破。针对国内大功率半导体激光器主要研究内容和关键技术进行了总结,在外延片结构中广泛采用应变量子阱结构、无铝有源区宽波导大光腔结构及非对称波导结构来提高端面光学灾变损伤光功率密度,还从腔面光学膜、器件封装、器件可靠性、光束整形与耦合以及器件应用等几个方面给予介绍。     

Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies

Integrated passives have become increasingly popular in recent years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context, particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). IPDs combine different passive components (R,L ,C ) in one subcomponent to be assembled in one step by standard technologies like surface mount device (SMD) or flip chip. In this paper, the wafer level thin film fabrication of integrated passive devices (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization, as well as results from the electrical characterization will be discussed.     

Parameterized physical compact thermal modeling

This paper presents a compact thermal modeling (CTM) approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing a CTM example with a BCI model for a benchmark ball grid array single-chip package under the same standard set of boundary conditions. In essence, the presented CTM method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging and three-dimensional integration.     

Flip chip die attach development for multichip mechatronics powerpackages

New package innovations are needed to address the next generation system requirements of the automotive market. Enhanced system functionality from semiconductor components and overall cost reduction demands drive multichip package solutions. The use of semiconductor devices to switch, control and monitor high current loads will integrate logic and power devices on a common substrate with requirements for effective power dissipation, current carrying capability and fine width conductor features for the control device and interconnections. To achieve these goals Motorola's Advanced Interconnection Systems Laboratory, Munich, has developed a new package concept, a multichip mechatronics power package, utilizing flip chip die attach technology and electroplated eutectic SnPb solder bumps. With the goal to deliver an advanced package platform to cover different power levels in the system architecture,the several substrate technologies were evaluated     

Robust Finite Element Model for the Design of Thermoelectric Modules

Thermoelectric devices for power generation have been receiving increased attention as an emerging sustainable energy technology because of recent advances in thermoelectric materials and the tremendous thermal resources available. Little focus has been given to the effective implementation of thermoelectric materials in power generation modules and efficient module design. With recent exploration into new module configurations, it is imperative that a comprehensive model be developed as a design tool. A new three-dimensional, device-level, multiphysics modeling technique is developed for the purposes of designing and evaluating thermoelectric module configurations. Using the new model, we identify and explore several geometric parameters which are critical to module performance. The impact on device performance of solder, ceramic interface, and electrical contact thickness, as well as the leg spacing, is evaluated for a standard unicouple configuration. Results are compared to the standard one-dimensional constant property models commonly used in thermoelectric module design.     

Vacuum electronics

This paper explores the recent history and diversity of this remarkable technology, with emphasis on recent advances in the more traditional device types (traveling-wave tube and klystron), as well as more recent innovations such as the microwave power module, inductive output amplifier, fast-wave devices, ultrahigh-power sources, and RF vacuum microelectronics. These advances can be credited to a combination of device innovation, enhanced understanding gained through improved modeling and design, the introduction of superior materials and sub-assembly components and the development of advanced vacuum processing and manufacturing techniques     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

电子封装技术发展现状及趋势

现今集成电路晶圆的特征线宽进入微纳电子时代,而电子产品和电子系统的微小型化依赖先进电子封装技术的进步,封装技术已成为半导体行业关注的焦点之一。主要介绍了近年来国内外出现的有市场价值的封装技术,详细描述了一些典型封装的基本结构和组装工艺,并指出了其发展现状及趋势。各种封装方法近年来层出不穷,实现了更高层次的封装集成,因而封装具有更高的密度、更强的功能、更优的性能、更小的体积、更低的功耗、更快的速度、更小的延迟、成本不断降低等优势,其技术研究和生产工艺不可忽视,在今后的一段时间内将拥有巨大的市场潜力与发展空间,推动半导体行业进入后摩尔时代。     

用于先进PCB制造工艺的叠层封装

在20世纪90年代,球栅阵列封装(BGA)和芯片尺寸封装(CSP)在封装材料和加工工艺方面达到了极限。这2种技术如同20世纪80年代的表面安装器件(SMD)和70年代通孔安装器件(THD)一样,在电学、机械、热性能、尺寸、质量和可靠性方面达到最大值。目前,三维封装正在成为用于未来采用的先进印制板(PCB)制造工艺的下一个阶段。它们可以分为圆片级封装、芯片级封装、和封装面。叠层封装(PoP)是一种封装面叠层封装类型的三维封装技术[15]。     

面向汽车应用的功率半导体器件与封装

汽车电子技术不断发展,越来越多的新器件、新封装应用在汽车中,这对汽车用功率半导体器件与封装提出很大挑战。文章介绍了不同种类功率半导体器件的特点,具体分析了当前主要的汽车用功率器件的分类、结构、封装与可靠性,并给出这一领域的发展现状。期望通过本综述能为发展国内汽车用功率半导体器件提供更广阔的视野。