RF Power Performance of Asymmetric-LDD MOS Transistor for RF-CMOS SOC Design

This letter presents a new asymmetric-lightly-doped-drain (LDD) metal oxide semiconductor (MOS) transistor that is fully embedded in a CMOS logic without any process modification. The radio frequency (RF) power performance of both conventional and asymmetric MOS transistor is measured and compared. The output power can be improved by 38% at peak power-added efficiency (PAE). The PAE is also improved by 16% at 10-dBm output power and 2.4 GHz. These significant improvements of RF power performance by this new MOS transistor make the RF-CMOS system-on-chip design a step further     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

Design methodology for the optimization of transformer-loaded RF circuits

In this paper, a design methodology for the optimization of transformer-loaded RF circuits is presented. The optimization procedure is based on a novel figure of merit for the integrated transformer (namely the transformer characteristic resistance), which was introduced to quantify its performance when operated as a tuned load. Using the proposed approach, a highly linear up-converter for 5-GHz wireless LAN applications was implemented in a 45-GHz-f/sub T/ SiGe HBT technology. The circuit achieved an output 1-dB compression point of 4.5 dBm and a power gain of 18 dB, while drawing only 34 mA from a 3-V power supply.     

Electro-thermal coupling analysis methodology for RF circuits

In this paper an electro-thermal co-simulation methodology suitable for RF circuits is presented. It circumvents traditional transient simulation drawbacks that arise when signals or magnitudes whose frequencies are separated orders of magnitude are present simultaneously in the simulated circuit. The accuracy of the proposed technique is verified experimentally by comparing simulation and measurements of the thermal coupling between an integrated power amplifier (PA) and a differential temperature sensor embedded in the same silicon die, using a 65 nm CMOS technology.     

Design of telecommunication electronic systems using a hardware/software co-design methodology

Design of real-time electronic systems is critical since these systems include performance constraints as part of their requirements. The goal is to map all functions of such systems on to distributed hardware/software architecture in such a way that all performance constraints can be met. Hardware/software codesign approaches are an important issue. The aim of this paper is to discuss a case study of an X25 system design using a hardware/software co-design methodology. Several alternatives are discussed with respect to their performance. A prototype of the X25 system, which correctly implements the system functionality while meeting real-time requirements, has been experimentally checked.     

Single-package integration of RF blocks for a 5 GHz WLANapplication

Transceivers for future digital telecommunications applications (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. Today's single-chip solutions for RF front-ends do not yield complete system integration. For example, they typically still need external components for impedance matching, for antenna switches, for power amplifiers and for RF bandpass filters (BPFs). Furthermore, problems of substrate coupling (either manifesting as analog crosstalk or as noise coupling from the digital part to the analog part on mixed-signal chip) become more important with increasing integration. A system-in-a-package (SiP) approach can address these problems. High quality components can be integrated in the package, avoiding lower quality on-chip passives or circumventing expensive chip technology adaptations. Virtually all external components can be integrated, as shown in this paper for the case of the bandpass filters and the impedance matching. Even the antenna is a candidate for integration in the package. Further, a clever chip partitioning can reduce the substrate coupling problem. Partitioning also allows using the best IC-technoiogy for each component. This paper reports on a fully integrated single-package RF prototype module for a 5 GHz WLAN receiver front-end, which is intended to demonstrate the concept of SiP integration. The approach, that is illustrated here with prototype RF blocks for a 5 GHz WLAN application, is implemented with a thin film multichip module (MCM-D) interconnect technology. This technology also allows the integration of high quality passive components. With these passives, low-loss filters can be implemented. The use of passives, filters and off-the-shelf, active, bare die components opens the way to successful system integration     

A time-harmonic inverse methodology for the design of RF coils inMRI

An inverse methodology is described to assist in the design of radio-frequency (RF) coils for magnetic resonance imaging (MRI) applications. The time-harmonic electromagnetic Green's functions are used to calculate current on the coil and shield cylinders that will generate a specified internal magnetic field. Stream function techniques and the method of moments are then used to implement this theoretical current density into an RF coil. A novel asymmetric coil operating for a 4.5 T MRI machine was designed and constructed using this methodology and the results are presented.     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

Fabrication of thick silicon nitride blocks for integration of RF devices

A fabrication process for the creation of thick (tens of micrometres) silicon nitride blocks embedded in silicon wafers has been developed. This new technology allows the use of silicon nitride as dielectric material for radio frequency (RF) circuits on standard CMOS-grade silicon wafers. Measurement results show that a performance similar to that of dedicated glass substrates can be reached     

Modeling and optimization of substrate resistance for RF-CMOS

A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.     

Automatic recognition of handprinted characters—The state of the art

Based on a study of the extensive literature in handprint recognition, this paper presents a survey in this challenging field. Recognition algorithms, data bases, character models, and handprint standards are examined. Achievements in the recognition of handprinted numerals, alphanumerics, Fortran, and Katakana characters are analyzed and compared. Data quality and constraints, as well as human and machine factors are also described. Characteristics, problems, and actual results on on-line recognition of handprinted characters for different applications are discussed. New emphases and directions are suggested.     

Implementation of Filter Bank–Based RF Transceiver for TV White Space

This paper presents a general‐purpose design scheme of a filter bank (FB)–based radio frequency (RF) transceiver that operates across the entire ultra‐high frequency (UHF) TV band from 470 MHz to 698 MHz and complies with the TV white space (TVWS) regulatory requirements. To this end, an intermediate frequency (IF) band‐pass filter (BPF) with a sharp skirt characteristic is considered as a solution for handling the incoming signals from a baseband modem. Specifically, an FB‐based BPF structure with four ceramic resonator filters that effectively rejects unwanted signals is proposed to extract a desired signal in the TV band. Achievable data rates of a cognitive radio system (CRS) employing the proposed FB‐based RF transceiver at the application layer are investigated in both wired and wireless environments. The service coverage of the CRS network is measured according to several modulation and coding schemes (MCSs) of the CRS. The results show that the coverage of a wireless network in a nearly open area can be extended by more than 9.3 km in the TVWS. Experimental results also confirm that the proposed FB‐based RF transceiver is adequate for utilization in TVWS applications.     

Circuit optimization: the state of the art

The authors review the current state of the art in circuit optimization, emphasizing techniques suitable for modern microwave CAD (computer-aided design). The main thrust in the field is currently the solution of realistic design and modeling problems, addressing such concepts as physical tolerances and model uncertainties. A unified hierarchical treatment of circuit models forms the basis of the presentation. It exposes tolerance phenomena at different parameter/response levels. The concepts of design centering, tolerance assignment, and postproduction tuning in relation to yield enhancement and cost reduction suitable for integrated circuits are discussed. Suitable techniques for optimization oriented worst-case and statistical design are reviewed. A generalized l_p centering algorithm is proposed and discussed. Multicircuit optimization directed at both CAD and robust device modeling is formalized. Tuning is addressed in some detail, both at the design stage and for production alignment. State-of-the-art gradient-based nonlinear optimization methods are reviewed with emphasis given to recent, but well tested, advances in minimax, l₁, and l₂ optimization     

Analysis of DC–RF Dispersion in AlGaN/GaN HFETs Using RF Waveform Engineering

This paper describes how dc–radio-frequency (RF) dispersion manifests itself in AlGaN/GaN heterojunction field-effect transistors when the devices are driven into different RF load impedances. The localized nature of the dispersion in the $I$– $V$ plane, which is confined to the “knee” region, is observed in both RF waveform and pulsed $I$–$V$ measurements. The effect is fully reproduced using 2-D physical modeling. The difference in dispersive behaviors has been attributed to the geometry of a trap-induced virtual-gate region and the resulting carrier velocity saturation being overcome by punchthrough effects under high electric fields.      

Automatic vehicle guidance and control—A state of the art survey

Highway automation is an attractive possible solution to some of the problems posed by an ever-increasing number of motor vehicles, as it would probably result in substantial increases in traffic-flow rates and a dramatic reduction in the numbers of highway accidents and fatalities. One practical system involves a roadway complex of the future, consisting of both automated and nonautomated roads, which will have evolved in an orderly and progressive manner from the roadway system of today. Only the main highways would be automated, and dual-mode vehicles would be used. The two major related technical areas in this framework are the physical characteristics of the various required subsystems for vehicle guidance and control and the optimum operation of the overall highway system. The elements of the former are divided into eleven categories: automatic longitudinal control, vehicle-spacing detection, communication systems, automatic lateral control, automatic merging control, controlled lane changing, vehicle propulsion, system decision-making capability, compatible manual mode, automatic vehicle checkout, and evolutionary developments. The role and state of the art of each category are discussed in detail, together with the complex interrelationships which exist among categories. Although some research has been accomplished, substantial future research and development progress will be necessary before an automated highway system is a practical reality.     

A New 12-Term Open–Short–Load De-Embedding Method for Accurate On-Wafer Characterization of RF MOSFET Structures

A new algorithm for open–short–load de-embedding of on-wafer $S$-parameter measurements is presented. Since in typical on-wafer RF transistor test-structures the imperfect grounding of the internal ports is the dominant source of crosstalk between ports, our proposed open–short–load approach resolving a 12-term error model is equally accurate as the current more general 15-term approach, which requires five dummy structures. To demonstrate this, experimental results obtained for six different increasingly sophisticated on-wafer correction schemes using 2–8 different de-embedding standards and resolving between 8–22 error terms, using $S$ -parameter data taken up to 110 GHz on 65- and 45-nm node MOSFET devices are compared.      

PWM regenerative rectifiers: state of the art

New regulations impose more stringent limits on current harmonics injected by power converters that are achieved with pulsewidth-modulated (PWM) rectifiers. In addition, several applications demand the capability of power regeneration to the power supply. This work presents the state of the art in the field of regenerative rectifiers with reduced input harmonics and improved power factor. Regenerative rectifiers are able to deliver energy back from the dc side to the ac power supply. Topologies for single- and three-phase power supplies are considered with their corresponding control strategies. Special attention is given to the application of voltage- and current-source PWM rectifiers in different processes with a power range from a few kilowatts up to several megawatts. This paper shows that PWM regenerative rectifiers are a highly developed and mature technology with a wide industrial acceptance.     

The state of the art in interplanetary Internet

Developments in space technologies are enabling the realization of deep space scientific missions such as Mars exploration. Interplanetary (IPN) Internet is expected to be the next step in the design and development of deep space networks as the Internet in the space. However, there are significant challenges to be addressed for the realization of this objective. This article captures the current state of the art and open research challenges, and intends to motivate researchers around the world to tackle these challenging problems and help realize the IPN Internet.     

Pension plans: The state of the art

The effect of termination of employment on pension benefits has become a matter of grave concern to engineers and scientists in the United States, particularly to those in the professions served by IEEE. In many cases during the postwar years, the decision to transfer from one employer to another has been a voluntary act of the professional worker and he could measure the cost of losing future pension benefits against the advantages of taking a new job. But within the last two years, a major change has occurred in the space and defense industries and their suppliers, which are so largely dependent upon government support of scientific and engineering work. In addition to discussing current pension practices in the United States, this report includes a review of activities by societies in this field, and the limitations imposed by legal and economic forces.