CDMA2000中的Turbo码的改进

本文提出了第3代移动通信系统CDMA2000标准中采用的Turbo码编码和译码的改进算法。通过Matlab仿真对卷积码和改进后的Turbo码在CDMA2000前向信道中的性能比较分析,证明改进后的Turbo码性能优异并能够通过减少迭代次数从而减轻译码复杂度。     

基于MAX-Log-MAP算法和DSP芯片的Turbo译码器

Turbo码又称为并行级联卷积码,其重要的特性就是实现了伪随机编码的思想,但要实现译码低误码率却要以降低整个编译码系统的效率和增加延时为代价。因此,本文通过分析Turbo码迭代译码原理和MAX-Log-MAP算法,根据性能要求和可行性考虑,以DSP芯片ADSP-TS101和MAX-Log-MAP译码算法来实现Turbo译码器的设计,实验结果表明,该系统误码率较低、延时性能符合要求,工作稳定。     

石油勘探测井仪数据传输实现方法

介绍双侧向石油勘探测井仪中,一种以ＭＣＳ－５１系列单片机的串行通信口为核心,采用基带脉冲编码传输一双极性归零脉冲 传输方式构成的数据传输系统。阐述了该系统的设计思想和实现方法,详细分析了该系统的工作原理和单极性不归零码与双极性归零码的相互转换方法。     

基于FPGA的Turbo码数据传输系统的实现

Turbo码是在低信噪比条件下具有良好纠错性能的信道编码,以与香农限仅差0.7 dB的特征而受到了科学研究者的广泛关注.目前,采用Turbo码实现大量数据的传输已经成为了无线通信传输协议的标配.介绍了Turbo码及其FPGA的实现,深入分析了Turbo码的解码理论与算法.首先,分析了Turbo码的编码流程及特性.其次,介绍了Turbo码的解码流程,并且讨论了在其解码过程中运用的Max Log MAP算法.最后,采用现场可编程逻辑门阵列(FPGA)硬件平台实现Turbo码的实时数据传输系统,并取得了良好的结果.     

Turbo码的并行算法研究

不同于传统的Turbo码,该文基于扩展咬尾递归系统卷积码(extended tail Biting recursive systematic,ETB-RSC)的思想,提出了一种并行的扩展咬尾Turbo码(parallel extended tail biting turbo code,PE-TBTC),它通过将接收序列分为若干子序列并行译码来显著提高译码速率。理论分析和仿真结果表明,PE-TBTC译码结构在不降低系统性能的前提下,以牺牲一定的硬件资源为代价,可以成倍地缩短译码所需时间。     

Ka频段固定卫星通信Turbo码性能仿真

使用Ka频段是卫星通信系统解决信道拥挤和提高系统容量的有效途径.为了提高Ka频段卫星通信的传输性能,本文在对Ka频段固定卫星通信信道进行分析的基础上,提出了一种适合该信道的Turbo码编译码方案,译码时通过使用修正的信道可靠性常数极大地提高了译码性能.最后,利用Ka固定卫星通信信道模型对该Turbo码方案性能进行了仿真.仿真结果表明,本文采用的Turbo码方案与采用相同码率的卷积码和卷积级联码方案相比,所带来的增益大于1.5 dB.     

基于Turbo码的卫星通信系统仿真研究

介绍了一种基于Turbo码的仿真方法。对Turbo码在卫星通信系统中的应用进行了较为详细的仿真建模和性能分析,设计了Turbo码的编码和译码器部分,并对仿真过程中的关键问题加以分析,通过仿真结果与理论比较,验证了仿真的正确性。     

基于ADSP-BF533的卷积码Viterbi译码算法实现

在通信系统中,接收机需要对信道编码进行译码,为了提高信道效率,一般采用具有纠错能力的纠错码来实现编码。在卫星通信中,一般采用卷积码内码和级联码外码联合纠错。首先叙述了卷积码的概念及其译码方法,接着对译码过程进行分析,提出了基于ADSP-BF533的实现方法,最后给出了实验方法及结果。     

基于软件无线电的Turbo码编码通信系统实现

为保障和提高无线信道下的数据传输可靠性和灵活性,基于通用软件无线电外设（USRP）平台设计和实现了以Turbo码作为信道编码方案的通信系统.系统发射机可采用1/2或1/3码率的Turbo码对传输数据进行编码,接收机通过软解调方法和软输入软输出的Max-Log-MAP迭代译码算法获得编码增益.仿真与测试结果表明,采用Turbo码作为编码方案可有效对抗噪声和衰落,降低传输误比特率,进而提高无线通信系统的可靠性.此外,通过文件传输等应用,进一步验证了本系统的可行性.     

Turbo码译码器的DSP实现

Turbo码以其优越的性能在通信系统中越来越受到人们的重视.由于Turbo码译码算法的复杂性,译码器通常需占用大量的存储空间和较长的运算时间,难以满足实际系统的要求.本文在深入研究Max-Log-MAP译码算法的基础上,对该算法进行了合理优化,提出了一种基于DSP的高效的软件实现方法.基于此方法实现的Turbo码译码器具有较低的误码率和较小的译码时延,在语音通信和数据通信中具有广泛的应用前景.     

Simulation and visualization of the Viterbi decoder using a spreadsheet

This paper demonstrates that a spreadsheet is an excellent tool for the simulation of the Viterbi decoder for educational purposes. Spreadsheet programming is streamlined by using complex number representations for metrics computation, allowing two values associated with each state at each time to be stored in a cell, thus providing a one-to-one correspondence between the spreadsheet cells and the nodes in the trellis diagram. The decoded path is plotted in a trellis diagram on the same spreadsheet so that the results can be readily visualized and examined. Either soft-decision or hard-decision decoding can be performed. A simple convolutional code of rate 1/2 and constraint length 3 is used for illustration, but the spreadsheet program is structured in such a way that it can be readily modified to simulate other codes.     

Inner code assisted parallel concatenated single parity check codes

This paper proposes a novel coding scheme to improve the performance of multidimensional parallel concatenated single parity check (PCSPC) codes. The high error floor of PCSPC codes prevents clear turbo cliff to be seen in the bit‐error rate (BER) performance. Based on the product accumulate type‐I (PA‐I) coding scheme, which adds serially an accumulator to the existing PCSPC code structure, our coding scheme considers a wide range of rate‐1 recursive systematic convolutional (RSC) codes replacing the accumulator. The convergence behavior of the proposed iterative decoding is monitored and analyzed using an extrinsic information transfer (EXIT) chart. It has been revealed from the EXIT chart analysis that the proposed coding scheme has a lower convergence threshold than the PA‐I coding scheme, especially when using a lower code rate PCSPC code as the outer code. For the 2D PCSPC(3,2) code with the code rate 0.5, the proposed coding scheme has a convergence threshold of 0.47 dB, whereas the convergence threshold of the PA‐I coding scheme is 0.81 dB. The convergence threshold of the proposed coding scheme is closer to theoretical limit (0.28 dB away from the theoretical limit) than that of the PA‐I coding scheme (0.62 dB away). However, for PCSPC codes with a higher code rate, the performance improvement of the proposed coding scheme with respect to the PA‐I coding scheme becomes smaller. A series of simulations is carried out to investigate the performance of the proposed coding scheme, and the simulation results show that better performance is achieved by using the proposed coding scheme compared with the PA‐I coding scheme. The simulation results show good consistency with the convergence threshold obtained from the EXIT chart, as the difference is only within 0.34 dB in all the evaluated cases. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Viterbi decoder (VD) is the majority used decoder for convolutional codes which play a role in WLAN and WSN applications. The trellis in VD needs proper analysis to calculate the metric at each stage to obtain a shortest path from every state to the next state. Existing techniques in VD design are namely (a) pipelined architecture, (b) modular ACS and buffers technique, and (c) quasi cyclic trellis technique. The key challenge of the VD trellis circuit is to attain high throughput and better latency performance with low power consumption without affecting hardware complexity of VD. This paper presents several of conventional methods used in VD. We also proposed a new method for VD with K the constraint length as multiple of M, the radix in trellis to calculate the shortest survival path to travel in trellis. The proposed VD is simulated using Xilinx. Use of a trace back approach in the proposed Viterbi decoder with capacitive and resistive feedback yields better throughput, latency, and power consumption with respect to other techniques. The static power outputs obtained in RE, shift update, and selective update methods using Libero IDE are also compared.     

Linear block codes

The article discusses systematic cyclic linear block codes. A block code uses an encoder that accepts a block of message symbols, and generates a block of code word symbols at the output. This type is in contrast to a convolutional code when the encoder accepts a continuous stream of symbols and similarly generates a continuous encoded output stream. A code is linear if the addition of any two valid code words results in another valid code word. Similarly, a code is cyclic if a circular shift of any valid code word results in another valid code word. The term systematic is used for codes in which the code word contains the message symbols in an unaltered form. Systematic code words are formed by appending additional symbols to the message. These additional symbols are called redundancy or parity symbols. The term symbols as used in this article denotes the individual elements of a code word. In a binary code, the symbols are bits and in a non-binary code, the symbols are collections of bits (e.g., bytes)     

多相互补码及其对多音频信号峰值因子的减小作用

本文研究了一种利用于互补自相关函数矩阵构造多相互补码对的方法,并给出了产生核心长度等于10的多相互补码对的例子。对于每一个核心长度,通过改变有关参数可以获得多个多相互补码对,而Golay互补码可以被认为是多相互补码的一个二相子类。提出了利用多相互补码来构成多音频信号以降低其峰值因子。仿真结果表明,它们对应的峰值因子小于或等于6dB,且和音频数无关,和理论分析相吻合。从仿真结果还可看出二进制Golay互补码能够产生对称的多音频信号。     

Performance enhancement using forward error correction on powerline communication channels

The use of forward error correction (FEC) coding is investigated, to enhance communication throughput and reliability on noisy power line networks. Rate one-half self-orthogonal convolutional codes are considered. These codes are known to be effective in other environments, and can be decoded inexpensively in real-time using majority logic decoders. Extensive bit and packet error rate tests were conducted on actual, noisy in-building power line links. Coding gains of 15 dB were observed at 10^-3 decoded bit error rates. A self-orthogonal (2, 1, 6) convolutional code with interleaving to degree 7 was particularly effective, and was implemented as a VLSI microelectronic chip. Its use improved data throughput and packet error rates substantially, at data transmission rates of 9,600 bits/s     

基于FPGA的Turbo译码器设计

Turbo码良好的纠错性能为众多研究者所公认,其相关理论和实现技术一直是该领域的研究热点。本文主要围绕如何用FPGA实现Turbo码译码器,介绍了Turbo码迭代译码的硬件实现算法以及流水线译码概念,并利用Altera的Flex10k10芯片实现了该译码器。性能测试实验表明,该基于FPGA实现的译码器最高速率可达到8Mbps,性能相比于理论译码器性能下降控制在0.5dB以内,具有广阔的应用前景。