Junction Field-Effect Transistors Based on PdSe2/MoS2 Heterostructures for Photodetectors Showing High Responsivity and Detectivity

2D materials have shown great promise for next-generation high-performance photodetectors. However, the performance of photodetectors based on 2D materials is generally limited by the tradeoff between photoresponsivity and photodetectivity. Here, a novel junction field-effect transistor (JFET) photodetector consisting of a PdSe₂ gate and MoS₂ channel is constructed to realize high responsivity and high detectivity through effective modulation of top junction gate and back gate. The JFET exhibits high carrier mobility of 213 cm² V⁻¹ s⁻¹. What is more, the high responsivity of 6 × 10² A W⁻¹, as well as the high detectivity of 10¹¹ Jones, are achieved simultaneously through the dual-gate modulation. The high performance is attributed to the modulation of the depletion region by the dual-gate, which can effectively suppress the dark current and enhance the photocurrent, thereby realizing high detectivity and responsivity. The JFET photodetector provides a new approach to realize photodetectors with high responsivity and detectivity.     

Giant and Nonvolatile Control of Exchange Bias in Fe3GeTe2/Irradiated Fe3GeTe2/MgO Heterostructure Through Ultralow Voltage

The discovery of van der Waals magnets has provided a new platform for the electrical control of magnetism. Recent experiments have demonstrated that the magnetic properties of van der Waals magnets can be tuned by various gate modulations, although most of them are volatile and require gate voltages no lower than several volts. Here, the realization of nonvolatile control of exchange bias and coercive fields in Fe₃GeTe₂/MgO heterostructures, and the gate voltage is as low as tens of mV which is two orders of magnitude smaller than those in previous experiments is presented. The discovery of an ionic-irradiated phase formed in Fe₃GeTe₂ by MgO sputtering revealed that an exchange bias effect can be obtained in this heterostructure and tuned from ≈700 to 0 Oe through voltages ranging from 5 to 20 mV. Owing to the high stability of oxidized Fe₃GeTe₂, the voltage-driven oxygen incorporated into Fe₃GeTe₂ from the irradiated phase induces a nonvolatile magnetism modulation that can be retained after turning off the gate voltage. These findings demonstrate a methodology to modulate the magnetism of van der Waals magnets, opening new opportunities to fabricate all-solid, long-retention, and low-dissipation nano-electronic devices using van der Waals materials.     

Gate‐Induced Massive and Reversible Phase Transition of VO2 Channels Using Solid‐State Proton Electrolytes

The use of gate bias to control electronic phases in VO₂, an archetypical correlated oxide, offers a powerful method to probe their underlying physics, as well as for the potential to develop novel electronic devices. Up to date, purely electrostatic gating in 3‐terminal devices with correlated channel shows the limited electrostatic gating efficiency due to insufficiently induced carrier density and short electrostatic screening length. Here massive and reversible conductance modulation is shown in a VO₂ channel by applying gate bias V_G at low voltage by a solid‐state proton (H⁺) conductor. By using porous silica to modulate H⁺ concentration in VO₂, gate‐induced reversible insulator‐to‐metal (I‐to‐M) phase transition at low voltage, and unprecedented two‐step insulator‐to‐metal‐to‐insulator (I‐to‐M‐to‐I) phase transition at high voltage are shown. V_G strongly and efficiently injects H⁺ into the VO₂ channel without creating oxygen deficiencies; this H⁺‐induced electronic phase transition occurs by giant modulation (≈7%) of out‐of‐plane lattice parameters as a result of H⁺‐induced chemical expansion. The results clarify the role of H⁺ on the electronic state of the correlated phases, and demonstrate the potentials for electronic devices that use ionic/electronic coupling.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

Modeling the effect of thin gate insulators (SiO2, SiN,Al2O3 and HfO2) on AlGaN/GaN HEMT forward characteristics grown on Si,sapphire and SiC

GaN-based high electron mobility transistors (HEMTs) with a Schottky metal gate have been demonstrated to be an excellent candidate for high frequency, high temperature and high power applications. Nevertheless, their typical (and virtually inevitable) high gate leakage current, severely limits gate voltage swing, output power and breakdown voltage. GaN metal–insulator –semiconductor HEMTs or MIS-HEMTs (formed by introducing a thin dielectric film between the gate metal and semiconductor) is one of the effective solutions that reduce gate leakage and improve device performance. In this work, we evaluate the effect that the introduction of this gate insulator has on the on-state of the HEMT. For this reason, we develop a complete set of compact closed-form expressions for the evaluation of on-resistance, drain and saturation current and transconductance for a MIS-HEMT. This physical-based model describes the mobility in a 2D electron gas channel by means of optical phonon scattering and is explored with insulators based on SiO₂, SiN_x, Al₂O₃, and HfO₂.     

Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO₂ gate dielectric.     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

Gate‐Controlled Energy Barrier at a Graphene/Molecular Semiconductor Junction

The formation of an energy‐barrier at a metal/molecular semiconductor junction is a universal phenomenon which limits the performance of many molecular semiconductor‐based electronic devices, from field‐effect transistors to light‐emitting diodes. In general, a specific metal/molecular semiconductor combination of materials leads to a fixed energy‐barrier. However, in this work, a graphene/C₆₀ vertical field‐effect transistor is presented in which control of the interfacial energy‐barrier is demonstrated, such that the junction switches from a highly rectifying diode at negative gate voltages to a highly conductive nonrectifying behavior at positive gate voltages and at room temperature. From the experimental data, an energy‐barrier modulation of up to 660 meV, a transconductance of up to five orders of magnitude, and a gate‐modulated photocurrent are extracted. The ability to tune the graphene/molecular semiconductor energy‐barrier provides a promising route toward novel, high performance molecular devices.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

Electrical Characteristics of Triple‐Gate RSO Power MOSFET (TGRMOS) with Various Gate Configurations and Bias Conditions

In this paper, we propose a triple‐gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage (BV_DS) and on‐state current (I_D,MAX), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer (SiO₂) of a conventional RSO power MOSFET is changed to a multilayered insulator (SiO₂/SiN_x/TEOS). The inserted SiN_x layer can create the selective etching of the TEOS layer between the gate oxide and poly‐Si layers. After additional oxidation and the poly‐Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as BV_DS and I_D,MAX, simulation studies are performed on the function of the gate configurations and their bias conditions. BV_DS and I_D,MAX are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15‐V gate voltage. This I_D,MAX variation indicates the specific on‐resistance modulation.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Few‐Layered PtS2 Phototransistor on h‐BN with High Gain

The very recently rediscovered group‐10 transition metal dichalcogenides (TMDs) such as PtS₂ and PtSe₂, have joined the 2D material family as potentially promising candidates for electronic and optoeletronic applications due to their theoretically high carrier mobility, widely tunable bandgap, and ultrastability. Here, the first exploration of optoelectronic application based on few‐layered PtS₂ using h‐BN as substrate is presented. The phototransistor exhibits high responsivity up to 1.56 × 10³ A W^?1 and detectivity of 2.9 × 10¹¹ Jones. Additionally, an ultrahigh photogain ≈2 × 10⁶ is obtained at a gate voltage V _g = 30 V, one of the highest gain among 2D photodetectors, which is attributed to the existence of trap states. More interestingly, the few‐layered PtS₂ phototransistor shows a back gate modulated photocurrent generation mechanism, that is, from the photoconductive effect dominant to photogating effect dominant via tuning the gate voltage from the OFF state to the ON state. Such good properties combined with gate‐controlled photoresponse of PtS₂ make it a competitive candidate for future 2D optoelectronic applications.     

Highly-sensitive solution-processed 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) phototransistors for optical sensing applications

A highly-sensitive organic phototransistor, based on solution-processed 2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene (diF-TESADT) was fabricated and investigated for an optical sensing element. The phototransistor based on thin crystalline grains of diF-TESADT exhibited a significant threshold voltage (V_TH) shift under a white light illumination in which the response time was estimated to be <0.5 s and a current modulation greater than 10⁶. It was found that the V_TH shift can be further enlarged by an additional gate bias, achieving very high light responsivity >10³ A/W at 0.17 mW/cm² and I_PH/I_DARK ratio higher than 10⁶. Also, by applying an erase gate bias, fast recovering of V_TH to the initial position was possible. This phenomenon can be ascribed to the trapping and de-trapping of photo-generated carriers at the organic channel/dielectric interface, while the amount of trapped carriers can be also modulated simultaneously by the gate bias. This investigation identifies that the solution-processed diF-TESADT phototransistors can be used for large-area and low-cost optical sensors and memory applications. In particular, it can be claimed that performance improvement by a gate bias represents a universal method applicable to the organic phototransistors.     

A methodology for the implementation of MOSFETs with a high-k dielectric gate material on the design of 90 nm technology circuits

Up to date, MOSFETs have been made through well established techniques that use SiO₂ as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO₂ as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO₂ is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO₂ devices. A cell layout is provided and the DRAM circuit characteristics are also presented.     

Enhancement of power conversion efficiency of PTB7:PCBM-based solar cells by gate bias

We designed and fabricated poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl]] (PTB7): [6,6]-phenyl-C70-butyric-acid-methyl-ester (PC₇₀BM)–based solar cells with gate electrodes, which can introduce an additional electric field within the devices just as in organic thin film transistors (OTFTs). Our proposed realize the simple and convenient modulation of electric field within the device, and power conversion efficiency (PCE) of 8.1% is reached at 2.0 V gate bias, significantly higher than the PCE of 6.8% at the case of no gate structure. By calculating the carrier mobility and the rate of exciton dissociation efficiency in detail, the role of electric field to the exciton dissociation and carrier transport was investigated, respectively. Meanwhile, the feasibility of the proposed device structure in practical application was discussed. The results suggest that such a gate structure has a great of prospects in achieving high efficiency polymer solar cells.     

Lateral WSe2 Homojunction through Metal Contact Doping: Excellent Self-powered Photovoltaic Photodetector

Here an IR-heating chemical vapor deposition (CVD) approach enabling fast 2D-growth of WSe₂ thin films is reported, and the great potential of metal contact doping in building CVD-grown WSe₂-based lateral homojunction is demonstrated by contacting with TiN/Ni metals in favor of holes/electrons injection. Shortening nanosheet channel to ≈2 µm leads to pronounced enhancement in the performance of diode. The fabricated WSe₂-based diode exhibits high rectification ratios without the need of gate modulation and can work efficiently as photovoltaic cell, with maximum open circuit voltage reaching up to 620 mV and a high power conversion efficiency over 15%, empowering it as superb self-powered photodetector for visible to near-infrared lights, with photoresponsivity over 0.5 A W⁻¹ and a fast photoresponse speed of 10 µs under 520 nm illumination. It is of practical significance to achieve well-performed photovoltaic devices with CVD-grown WSe₂ using fab-friendly metals and simple processing, which will help pave the way toward future mass production of optoelectronic chips.     

A novel gate insulator for flexible electronics

Field effect transistors using a poly(triaryl amine) p-channel organic semiconductor in conjunction with anodised aluminium oxide as the gate insulator (Al₂O₃ on Al) are demonstrated. Anodised films are pinhole-free, homogenous oxide layers of precisely controlled thickness. The anodisation process requires no vacuum steps; anodised Al₂O₃ is insoluble in organic solvents, and Al films are cheaply available as laminates on flexible substrates. Anodised Al₂O₃ is confirmed to have high gate capacitance (≈60 nF/cm²) and electric breakdown strength (>3 MV/cm in the working device). This property profile answers to the demands on gate insulators for flexible electronics applications.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.