Turbo码并行译码中无冲突交织器设计方案

交织器的结构可以影响到Turbo码的最小码距,进而影响其编码增益,最终对误比特率产生较大影响。交织器的主要功能就是随机化输入信息码序列,并让两个子编码模块在任何时刻,不会同时输出码重较轻的码字。交织器的随机性直接影响着Turbo码并行译码性能,针对现有无冲突交织器中随机性较小的特点,引入行内、行间交织等处理方式,进一步增加了交织表的随机性,以此提高Turbo码并行译码的性能,并给出了行内、行间交织设计实例。     

Turbo码的一种并行译码方案及相应的并行结构交织器研究

Turbo码基于MAP算法译码的递推计算所引入高的译码延迟限制了Turbo码在高速率数据传输中的应用。为了解决这个问题,该文提供了一种降低译码延迟的并行译码方法。并行处理方案的实现必须通过适当的交织以避免两个译码器对外信息读写的数据冲突。该文在分析了任意无冲突交织方式可能性的存在之后,给出了设计任意地适用于并行处理方案的S随机交织器的方法。仿真验证了并行译码方案的误比特性能。     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

低复杂度Turbo码译码并行实现

MAX-LOG-MAP是Turbo码译码算法的简化算法,本文提出了该算法的并行阵列集成电路实现结构,给出阵列的数据流向和译码算法在阵列中的计算过程,分析了阵列结点联接关系和数据存贮结构,以及数据运算之间的简单时序关系.通过计算机仿真,证明了这种并行实现结构的正确性.     

基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

WCDMA中Turbo码算法及质数交织器的研究

介绍了WCDMA中所采用的Turbo码编码结构中、质数交职器、MAP解码算法，进而给出不同内交织结构下，基于MAP算法的Turbo码译码性能仿真曲线与相关结论。     

Turbo码随机交织器的设计与实现

Turbo码中交织器性能的优劣将直接影响到Turbo码的译码性能.在分析交织器的设计准则和类型的基础上,利用m序列的遍历性,设计了一种基于m序列的随机交织器,并给出了基于FPGA的硬件实现方案.仿真结果表明,该随机交织器在实现输入数据随机分布方面性能优异,并降低了Turbo码的译码延迟.     

QPP内交织器的架构设计与实现

为达到较高的吞吐率,在Turbo码并行译码时,需采用二次置换多项式(QPP)内交织器.通过理论分析,提出一种新的QPP内交织器实现方法与架构.相比现有的实现方法,提出的实现方法复杂度降低,计算简单,资源占用减少.软件仿真结果证明了该方法的正确性.     

LTE-Advanced标准中一种基于反向重算的低存储容量Turbo码译码器结构设计

在LTE-Advanced标准中,为满足移动环境下的低功耗要求,低存储容量的译码器结构设计引起了广泛关注.本文在分解Turbo码网格图的基础上,研究了前向状态度量的反向重算方法,提出了一种基于反向重算的低存储容量译码器结构设计方案.在Log-MAP算法下研究了一种适合反向重算的修正雅可比对数式实现方法,推导了反向重算的数学表达式,并给出了实现结构.结果表明,所涉及的反向重算译码结构,以很小的冗余计算为代价将存储容量降低了50%,译码性能非常接近Log-MAP算法,在冗余计算复杂度、存储容量和译码性能指标上具有更好的均衡性.     

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding

Emerging digital communication applications and the underlying architectures encounter drastically increasing performance and flexibility requirements. In this paper, we present a novel flexible multiprocessor platform for high throughput turbo decoding. The proposed platform enables exploiting all parallelism levels of turbo decoding applications to fulfill performance requirements. In order to fulfill flexibility requirements, the platform is structured around configurable application-specific instruction-set processors (ASIP) combined with an efficient memory and communication interconnect scheme. The designed ASIP has an single instruction multiple data (SIMD) architecture with a specialized and extensible instruction-set and 6-stages pipeline control. The attached memories and communication interfaces enable its integration in multiprocessor architectures. These multiprocessor architectures benefit from the recent shuffled decoding technique introduced in the turbo-decoding field to achieve higher throughput. The major characteristics of the proposed platform are its flexibility and scalability which make it reusable for all simple and double binary turbo codes of existing and emerging standards. Results obtained for double binary WiMAX turbo codes demonstrate around 250 Mb/s throughput using 16-ASIP multiprocessor architecture.      

Turbo码快速交织器的设计及其CPLD实现

针对目前Turbo码交织时延大影响编译码速率提升的缺陷，采用对m序列进行优选的方法设计了一种快速交织器，并基于CPLD给出硬件实现方案。仿真结果表明，该交织器在不增加编译码复杂度的情况下，一次迭代过程交织模块即能减少20％时间延迟．在时延和性能之间取得较好的折衷。     

Turbo解码算法的系统实现和性能

本文对Turbo解码算法的性能和系统实现进行了研究.从硬件实现复杂度和解码数据速率两个关键方面,对解码算法和系统实现提出了改进,进行了改进算法的性能仿真分析,并成功地在所开发的第三代移动通信系统中予以实现.针对Turbo码在第三代移动通信WCDMA系统中的具体应用,本文详细讨论了改进算法在系统中的硬件实现方案和性能结果.     

Turbo码中交织器的综合性能分析与设计

在Turbo码理论中,交织器占有重要地位。论文分析了Turbo码的编译码方案,阐明了交织器在Turbo码设计中的重要作用,提出了几种交织器的设计实现方法,并在仿真的基础上对其性能进行了分析。     

MPEG-4解码的并行处理优化

结合TI公司的TMS320DM320针对媒体处理并行数字信号处理结构特点,分析MPEG-4算法本身的实现,采用了流水线设计的方式,针对性地提出了基于DM320上的MPEG-4解码算法.分析了各个芯片内部资源的利用率,提出了未来优化的方向.     

基于CUDA的双二进制Turbo码并行译码方法

卫星回传信道数字视频广播(Digital Video Broadcasting-Return Channel over Satellite,DVB-RCS)标准中回传信道采用双二进制Turbo码作为前向纠错编码(Forwar Error Correctiong,FEC),为了提升译码算法的运算速度,在Max-LogMAP译码算法基础上,提出了基于统一计算设备架构(Compute Unified Device Architecture,CUDA)的图形处理器(Graphic Processing Unit,GPU)并行计算加速译码方法,其运算速度与中央处理器(Central Processing Unit,CPU)运行相比,提高了约20倍。     

3GPP WCDMA系统Turbo译码中交织解交织的FPGA实现方案

本文主要介绍了在第三代移动通信WCDMA系统中Turbo/MAP译码部分交织解交织模块的FPGA实现方案.该方案把交织图样的预计算和快速的硬件查表法巧妙相结合,从而有效地节省了Turbo码译码资源,缩短了译码时间.     

一种加速Turbo码译码实现的改进算法的研究

本文针对Turbo码在译码过程中复杂度相当大的缺点,提出了一种新的改进算法,通过对附加信息的门限判决而加快译码速度,从而降低了译码复杂度,提高了译码性能.此外,我们还给出了此门限值的理论确定方法.计算机模拟结果表明,采用所提出的改进算法与传统的最大后验概率译码算法相比,其译码性能和译码复杂度均有明显的改善.     

Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit

A study of the MPEG-2 video decoding standard in Main Profile @ Main Level has been performed, comparing the different solutions existing for the VLSI implementation of the basic functions (Huffman decoding, IDCT...) included in the standard. Afterwards, a new dynamically configurable architecture is proposed for the memory manager, which is necessary to deal with the large data flow inside the decoder. It is aimed at interfacing the external memory, arbitrating the access requests coming from the different decoding units and allowing generic memory requests through the definition of virtual addresses. It is shown that, by means of a particular data organization, the circuit requires an external memory, which is a 2-MB DRAM in fast page or EDO mode, accessible via a 64-bit bus. The memory manager works at 27 MHz and allows a real-time decoding for MP @ ML bitstreams. It has been synthesized in a 0.8-m two-metal CMOS technology and presents a total area of 5.4 mm2 for 6500 gates.     

Memory Power Reduction for High-Speed Implementation of Turbo Codes

Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.     

交织器的研究和在Turbo码中的应用

交织器不但在传输性能较差的无线信道中，提高了抗突发错误的能力，而且在Turbo码的设计中起到了重要作用。本文分析了几种交织器的基本原理并对其性能进行了比较，提出了今后交织器研究的重点。