Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology

This work presents a new method for the fabrication of buried microchannels, covered with porous silicon (PS). The specific method is a two-step electrochemical process, which combines PS formation and electropolishing. In a first step a PS layer with a specific depth is created at a predefined area and in the following step a cavity underneath is formed, by electropolishing of silicon. The shape of the microchannel is semi-cylindrical due to isotropic formation. The method allows accurate control of the dimensions of both PS and the cavity. The formation conditions of the PS layer and the cavity were optimized so as to obtain smooth microchannel walls. In order to obtain stable structures the area underneath the PS masking layer was transformed into n-type by implantation, taking advantage of the selectivity of PS formation between n- and p-type silicon. With this technique, a monocrystalline support for the PS layer is formed on top of the cavity. Various microchannel diameters with different thickness of capping PS layer were obtained. The process is CMOS compatible and it uses only one lithographic step and leaves the surface of the wafer unaffected for further processing. A microfluidic thermal flow sensor was fabricated using this technology, the experimental evaluation of which is in progress.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

A MEMS micromirror fabricated using CMOS post-process

This work describes the fabrication of a micromachined micromirror by the conventional 0.35 μm CMOS process and a simple maskless post-CMOS process. The micromirror contains a rectangular mirror plate and four pairs of serpentine supported beams, is integrated with a 1 × 4 demultiplexer and a four-stage charge pump circuits on a chip. Maskless dry and wet etching processes are the only requirement to suspend the structure. The primary limitation in the fabrication of microstructures has been overcome by the development of a hybrid processing technique, which combines both an anisotropic dry etch and an isotropic wet etch step. A highly reliable wet etching step with high selectivity between aluminum and sacrificial oxide is also reported. Experimental results reveal that the micromirror has a tilting angle of around 5° at operation voltage of 22.5 V and a dynamic response less than 5 ms. The surface properties of the CMOS micromirror, detailed process flows, measurement set-up and the experimental results are also presented in this work.     

A CMOS compatible process for monolithic integration of high-aspect-ratio bulk silicon microstructures

We report a CMOS compatible bulk micromachining method for the integration of high-aspect- ratio single crystal silicon MEMS （micro electromechanical systems） devices and signal conditioning circuit on a standard silicon wafer. The trench refilling and residual silicon removing techniques are used to acquire a proper electrical insulation between the different actuation and sensing elements situated on either fixed or movable parts of an MEMS device. To demonstrate the compatibility of the process, an integrated MEMS accelerometer was implemented. Test results show that the resistance between different elements of the device is larger than 1012 Ω. The electrical properties of the transistors that experienced MEMS fabrication agree well with those without ]VIEMS process, indicting the CMOS compatibility of the process.     

100‐MHz CMOS circuits directly fabricated on plastic using sequential laterally solidified silicon

Abstract— CMOS TFT circuits were fabricated on plastic using sequential laterally solidified silicon combined with a low‐temperature CMOS process. The unity‐gain frequencies of the best of NMOS TFTs are greater than 250 MHz, and the CMOS ring oscillators operate at 100 MHz. To the best of the authors' knowledge, these are the highest‐frequency circuits ever fabricated directly on plastic. This high‐performance CMOS‐on‐plastic process can be applied to the fabrication of AMLCD integrated drivers and AMOLED pixels on plastic substrates.     

Micromechanism fabrication using silicon fusion bonding

Silicon fusion bonding is studied as an enabling technology for the fabrication of microrobotic mechanisms. The effects of both surface activation technique and annealing temperature on bond strength are considered using a crack-opening technique. As part of the study, the relationship between patterned silicon feature size and the resulting bond strength is explored. Based on the experimental results, recommendations for an optimal silicon fusion bonding process for micromechanism fabrication are presented. The experimental results indicate that bulk silicon bonding strength can be achieved independent of feature size at temperatures as low as 300°C, with positive implications for micromechanism fabrication.     

A micromachined tunable resonator fabricated by the CMOS post-process of etching silicon dioxide

This work investigates the fabrication of a micromechanical tunable resonator using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-process of only one maskless wet etching. The post-process has advantages of easy execution and low cost. The post-process employs an etchant (silox vapox III) to etch the silicon dioxide layer to release the suspended structures of the resonator. The tunable resonator comprises a driving unit, a tuning unit and a sensing unit. The resonant frequency of the resonator can be tuned using a dc-biased electrostatic comb of linearly varied finger-length. Experimental results show that the resonant frequency of the resonator is about 4.8 kHz, and it has a frequency-tuning range of 6.8% at the tuning voltage of 0–25 V.     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

Micromachined silicon resonant strain gauges fabricated using SOIwafer technology

The optimum mode of double-ended tuning-fork-style resonators is a lateral vibration in the plane of the wafer. Lateral vibrations are typically excited using the comb drive approach, but this requires modification to the resonator structure. This paper reports a simple method for exciting and detecting lateral vibrations without modifying the resonator, thereby enabling the optimum dynamically balanced structure to be used. This approach uses plane electrodes positioned parallel to the resonator's tines to excite the vibrations while the change in resistance along the length of the resonator enables the vibrations to be detected. Test devices have been fabricated in single-crystal silicon using the buried oxide in silicon-on-insulator wafers as a sacrificial layer. The resonators are 340-μm long, 3-μm thick with tines 2-μm wide. The gap between the tines and the electrode is 2 μm. Visual inspection in a scanning electron microscope and electrical tests have confirmed the validity of this approach     

Qualitative and quantitative substance discrimination using a CMOS compatible non-specific NDIR microarray

A non-specific non dispersive infrared (NDIR) micro-optical gas detection system is presented. The system is based on a monolithic filter microarray (up to 16 non substance oriented elements) that is attached by flip-chip onto a matching microarray of thermopiles, configuring a compact CMOS compatible optical detector. The system aims to combine the stability of infrared optical devices and the versatility of electronic-nose approaches. The transmission spectra of the filters, multi-peaked and of broad band nature, are not oriented to any specific substance detection, and multivariate regression techniques are used to predict gas type and concentrations from the voltage pattern generated by the thermopile array. The ability of the system for substance discrimination has been proved by means of qualitative volatile identification (ethanol, isopropanol and acetone) and quantitative tests have been performed with CH₄ and CO₂ mixtures.     

Batch transfer of microstructures using flip-chip solder bonding

This paper describes a novel method for transfer and assembly of microstructures using sacrificial-layer micromachining and flip-chip bonding. The technique is performed at room temperature (cold weld) and at the back end of the process flow and may thus provide a commercially viable alternative to monolithic integration and costly hybrid packages. The transfer is achieved using break-away tethers and by cold welding (compression bonding) electroplated indium solder bumps to electroplated copper pads. Both high-aspect-ratio MEMS devices as well as surface-micromachined devices have been successfully transferred using this method with no observable misalignment between moving and stationary parts. The maximum tensile and shear stress the solder bond can withstand before failure is measured to be 11±3 MPa and 9±1 MPa, respectively. The contact resistance is measured to be of the order of 1.5 mΩ for a 65 μm×65 μm×4-μm indium bump     

Optimal performance of CMOS compatible IR thermoelectric sensors

This paper presents a theoretical and empirical study of the optimal performance of CMOS compatible infrared thermoelectric sensors with varying pixel area and different aspect ratio of the pixels for two possible sensor structures: cantilever and bridge types. Optimal performance is analyzed analytically, using simplifying assumptions. This analysis is verified by comparing with the exact simulations as well as by comparing with measured results. The resistance of optimized sensors in the sense of minimal noise equivalent power (NEP) is shown to be independent of aspect ratio, but proportional to the third root of the pixel area. The product of the optimal NEP and the square root of the time constant is shown to be constant with varying aspect ratios, while the same applies with the time constant to the power of 3/8 for varying areas. The measured sensors exhibit NEP's down to 13.5 nW in a 300-Hz bandwidth and time constants up to 30 ms     

Arrays of large-area, tip/tilt micromirrors for use in a high-contrast projector

Arrays of two-degree of freedom analog micromirrors are designed for use within an high-contrast projector and fabricated using a multi-user MEMS fabrication process. We demonstrate a novel way of optimizing the tradeoffs between tilt angle and mirror size by subdividing the mirrors into smaller functional subsections that move synchronously. The mirror design employs multiple mirrors within a gimbal frame. The frame rotates around one axis, and each mirror within the frame rotates around a perpendicular axis, resulting in two-degree of freedom rotation. The design employs specific electrode shapes to allow one-layer connections. Using these fabricated mirrors, simultaneous actuation of mirrors within a composite structure is achieved. A prototype array of fabricated mirrors is described, with 6 × 5 mirrors each of 160 μm × 160 μm forming one composite mirror of an array, giving total active area of 960 μm × 800 μm. The mirrors can achieve a maximum tilt angle of 2.25°. The fill factor of this design is 68%.     

3D surface topography and reflectivity of anisotropic etched silicon micromirrors for BioMEMS

This paper examines wet and dry fabrication of vertical micro-mirrors in (110) silicon for use in an innovative BioMEMS integrating gripping and micro force sensing functionalities. Wet anisotropic chemical etching in potassium hydroxide (KOH) and tetramethyl ammonium hydroxide (TMAH) with and without isopropanol alcohol (IPA) additive was examined. Deep Reactive Ion Etched samples were produced using inductive coupled process. 3D surface roughness of samples was examined using scanning electron microscope, interferometric profilometer and atomic force microscopy. An optic fiber displacement sensor was exploited to measure the reflectivity of uncoated or coated samples with evaporated metallic thin film. The research aimed to find optimal fabrication technique for fabricating vertical micro-mirrors in polymer based BioMEMS. TMAH etched silicon samples with surface roughness R _a = 15.1 nm showed highest reflectivity of all structures fabricated, reflectivity was more than doubled by adding a 10 nm layer of evaporated aluminum coating.     

MEMS单晶硅加热雾化芯片设计与制作

为实现高粘度液体的雾化,提出一种微机电系统(MEMS)单晶硅快速加热雾化芯片。对单晶硅加热芯片结构进行了设计,芯片为10 mm×10 mm的方形,布置了168个边长为500μm的方形雾化孔。通过ANSYS有限元软件进行了电—热耦合仿真,以评估其温度分布均匀性。衬底采用5×10~(-3)Ω·cm的4 in(l in=2.54 cm)N型(100)硅片,基于各向异性湿法腐蚀工艺完成了微孔阵列和芯片的制造。测试结果表明:室温下芯片电阻约为0.6Ω,且电阻值与温度呈正相关;芯片温度分布均匀,最低温与最高温相差约12.7%;施加3.7 V电压时,芯片在4 s内可升温至300℃,能够实现对甘油的快速雾化。该芯片结构和制作工艺简单,易于实现批量制造。     

基于OPC技术的单晶硅提拉过程控制研究

针对传统PID控制无法满足单晶硅提拉过程中电机转速的控制要求,以及PLC难以实现复杂控制算法的问题,本文采用OPC技术实现MATLAB与PLC之间的通信,在MATLAB中实现神经网络PID在线调节PID参数,采用OPC技术将结果传输给PLC,从而实现单晶硅提拉过程中的快速、准确控制。     

直拉硅单晶非均匀相变温度场最优控制

针对直拉硅单晶固液界面相变温度场的非均匀性导致晶体直径不均匀问题,提出一种基于偏微分方程(PDE)模型的温度场最优控制策略.考虑生长速率波动的影响,建立了一种改进的提拉动力学模型,确定了域边界演化动力学关系.研究基于抛物型PDE的时变空间域对流扩散过程的温度模型,描述了域运动在对流扩散系统上的单向耦合.针对无限维分布参数系统建模控制难问题,采用谱方法进行系统近似,选取整个空间域的全局和正交的空间基函数,通过Galerkin方法对无限维系统进行降维,获得了该系统的近似模型.采用线性二次型方法控制晶体生长温度,通过仿真实验对相变温度场模型进行验证.结果表明,优化后的模型能够获得较为平稳的晶体生长速率,减小了生长直径的波动,使得固液界面径向温度分布更加均匀,验证了该方法的有效性.     

Hydrophobic direct bonding of silicon reconstructed surfaces

The bonding of hydrophobic, reconstructed (001) Si surfaces obtained with high temperature H₂ processes has been studied with atomic force microscopy, low energy electron diffraction spectroscopy, X-ray reflectivity and bonding energy measurements. Surface reconstruction is shown to strongly affect bonding mechanisms. As a consequence, bonding energies of such surfaces are significantly higher, in the room temperature ?500 °C range, than those of “HF-last” surfaces.     

Direct bonding of titanium layers on silicon

Direct metal bonding is a key technology for 3D integration that will allow semiconductor industry to go beyond predicted problems of future ICs. In this paper, for the first time, we show room temperature direct bonding of titanium layers on silicon wafers at atmospheric pressure and ambient air. Transmission electron microscopy and spreading scanning resistance microscopy are used to investigate bonding interface. Several physical mechanisms of titanium–titanium interface sealing during subsequent thermal annealing are observed and compared to copper and tungsten in terms of bonding mechanism and temperature dependence.