A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

Analytical analysis of surface potential for grooved-gate MOSFET

The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner $\theta _0 $. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect (SCE) immunity.     

Performance and analytical modelling of halo-doped surrounding gate MOSFETs

Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor fieldeffect-transistors （MOS- FETs） to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson＇s equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Characteristics Analysis of Vertical Double Gate Strained Channel Heterostructure Metal-Oxide-Semiconductor-Field-Effect-Transistor

Since device feature size shrinks continuously, there appears various short-channel effects on the fabrication and performance of devices and integrated circuits. We present a vertical double gate （VDG） strained channel heterostrueture metal-oxide-semiconduetor-field-effect-transistor （MOSFET）. The electrical characteristics of the device with the effective gate length scaled down to 60nm are simulated. The results show that the drive current and transconductance are improved by 57.92% and 54.53% respectively, and grid swing is decreased by 36.83% over their unstrained counterparts. VDG MOSFETs exhibit a stronger capability to restrict short-channel-effects over traditional MOSFETs.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

As the channel length of metal-oxide-semiconductor field-effect transistors （MOSFETs） scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate （SG） nMOSFET is developed. The SchrSdinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The eentroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.     

A Closed-Form Model for Position-Dependent Potential across the Channel in DG-MOSFETs

A closed-form model for electrostatic potential distribution in the direction normal to the channel for double-gate （DG） MOSFETs is presented. The effects of doping （NA for nMOS） and minority carriers both are taken into account for the first time, in solving Poisson＇s equation analytically. Excellent agreement between model-predicted results and numerical device simulation is achieved for a wide range of body thickness, light or high channeldoping, under various bias conditions. This complete closed form for position-dependent potential distribution has wide applications for MOS compact modelling and device design.     

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.     

体硅、SOI及DSOI MOSFET器件级电、热分析

利用简化的半导体电学方程,数值模拟获得了各种电学参数的分布,并结合简化电阻模型,模拟了体硅、SOI及DSOI的MOSFET器件的温度场。结果表明MOSFET器件的沟道,特别是靠近漏的区域电场强度及电流密度等各项电、热特性参数在该区域变化剧烈,是最主要的热源区。     

A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

Energy relaxation of electrons impacts on channel quantization in nano-MOSFETs

The effects of the rising electron temperature due to the energy relaxation on the quantization of the inversion layer in a nano-metal–oxide–semiconductor field transistor (MOSFET) with p-type silicon substrate have been theoretically investigated via self-consistent solution to the coupled Schrödinger equation with considering quantum coupling effects and Poisson equation. The first quantized energy level in the inversion layer rises from 3.6 to 211.4 %, and the total number of the inversion channel electron decreases from 95.7 to 6.5 % relative to those neglecting energy relaxation of channel electrons when the channel electric field increases from 10 to 55 kV/cm. The output characteristic of MOSFET will be largely affected by the energy relaxation when the channel electric field is higher than 10 kV/cm. All these suggest that the energy relaxation of channel electrons should be considered in the modeling of MOSFETs for higher channel electric field.