可编程半导体抗浪涌保护器件

通过对各种半导体抗浪涌保护器件特点的比较，介绍了第四代抗浪涌保护器件(P61089)的工作原理，分析了他在程控交换机上对用户线接口线路(SLIC)板的保护机理，结果表明P61089在前三代半导体抗浪涌保护器件的基础上性能大为提高。最后给出了该器件两个关键参数的测试方法。     

双芯IGCT浪涌电流鲁棒性研究

作为晶闸管类器件,双芯集成门极换流晶闸管(Dual IGCT)必须具备的抗浪涌电流能力研究鲜见报道。基于多单元集成的器件仿真结构模型,揭示了Dual IGCT在浪涌电流下工作时,总电流在GCT-A部分和GCT-B部分间的分配比例会随晶格温度升高而减小。在此基础上,分析了寿命控制技术对Dual IGCT浪涌鲁棒性的影响。结果表明,增大GCT-B的载流子寿命可以提高器件的浪涌鲁棒性,但同时会增大器件的功耗;而在对GCT-B进行载流子寿命控制时,引入具有较大寿命对温度依赖系数的复合中心,可以有效提高Dual IGCT浪涌电流鲁棒性,同时不影响器件的其他性能。最后,提出了一种工艺成本较低的阳极短路Dual IGCT新结构,其在浪涌电流下的晶格温升与传统的Dual IGCT相比大幅减小(约150 K),呈现出极高的抗浪涌能力。     

半导体浪涌保护器基区参数探讨

讨论了半导体浪涌保护器件的基区宽度，着重分析了基区宽度与开通电压、静电电容、浪涌能力的关系，指出控制基区宽度，可有效地提高器件的浪涌能力，降低静电电容和开通电压     

提高多元胞结构半导体放电管浪涌能力的研究

讨论了半导体放电管能量损耗对其浪涌能力的影响.结果表明减小长基区宽度可以明显地降低器件的开通和通态能量损耗,从而有效提高器件的浪涌能力.     

功率肖特基二极管反向EOS量化检测及改善

由于抗反向过压或过流冲击能力不足而导致的功率肖特基势垒二极管(SBD)的潜在失效,会影响电路的可靠性,也是器件制造中最难解决的问题.根据SBD特点和应用要求,给出了静电放电(ESD)、反向浪涌电流冲击、单脉冲雪崩能量三种抗反向过电应力(EOS)能力的量化检测方法.针对三种检测方法的特点,明确了失效机理,并从工艺参数、器件结构等方面给出了解决办法.以2 A 100 V SBD芯片为例,通过器件仿真、流片验证,给出了通过p+保护环结深、p+结浓度、外延层厚度、保护环面积等工艺和结构参数改善ESD、反向浪涌电流冲击、单脉冲雪崩能量的方法.提出了一种p+-p-保护环的结构,可提高功率SBD的抗反向瞬态冲击特性.     

半导体放电管多元胞结构模型

在半导体放电管的版面设计上提出了多元胞结构版图 .对多元胞结构“短路模型”进行了理论分析和实验验证 ,结果表明合理设计多元胞版图尺寸和 P基区薄层电阻可以改善器件的转折导通特性和提高器件的抗雷电浪涌能力 ,从而为简化半导体放电管生产工艺提供了依据     

浪涌信号与防护方法

本详细地介绍了浪涌信号的危害与防护方法，给出了浪涌防护器的主要技术参数与要求，最后讨论了常用的浪涌防护器件。     

PoE交换机雷击浪涌防护设计

PoE（Power over Ethernet）交换机雷击浪涌防护设计在现阶段具有重要意义。本文分析了三种主要浪涌防护器件特性,比较其各自优缺点,在针对不同使用环境下PoE交换机的防护电路设计中,将三种防护器件分别组合使用,得到具体防护电路。最后,将所得电路进行雷击测试,测量经过防护电路之后的波形,最终证明,所设计电路能够起到抗雷击浪涌保护电路的作用。     

半导体放电管多元胞结构模型

在半导体放电管的版面设计上提出了多元胞结构版图.对多元胞结构“短路模型”进行了理论分析和实验验证,结果表明合理设计多元胞版图尺寸和P基区薄层电阻可以改善器件的转折导通特性和提高器件的抗雷电浪涌能力,从而为简化半导体放电管生产工艺提供了依据.     

一种新型AC浪涌电流限制器件STIL

ST公司新推出的浪涌电流限制器件STIL．集成了两个单向功率开关及控制驱动器．在抗噪扰能力．功率．损耗．尺寸和可靠性等方面．均优于NTC热敏电阻．SCR．Triac和继电器等传统元件。     

改进SSPD浪涌吸收能力的工艺研究

介绍了用于宽带快速信息传输系统的半导体瞬态浪涌保护器件（ＳＳＰＤ）在小的器件面积和小的器件电容情况下,提高ＳＳＰＤ浪涌吸收能力的工艺方法。理论分析和实验结果都说明,关键是减少基区总宽度,而在制备工艺中设法减少基区少子寿命的衰减也是有效措施之一。     

多元胞半导体电涌吸收器件的研究

设计并试制了一种多元胞结构的半导体电涌吸收器件（ＳＳＡＤ），旨在降低器件工作时的最高温度并提高其过浪涌能力。初步实验结果证明器件经历过电涌后，其失效率比单元胞有较显著的降低。     

玻璃钝化技术对半导体放电管抗浪涌能力的影响

半导体放电管是新一代抗浪涌保护器件，极问电容是其应用到高频环境下的一个限制因素。文章从半导体放电管的基本结构出发，介绍了用玻璃钝化技术去除放电管侧壁电容的方法。理论分析表明，在没有采用玻璃钝化技术时，流过放电管结底部的电流大于流过其侧壁的电流，因此，采用玻璃钝化技术对半导体放电管的抗浪涌能力影响不大。     

The MAJIC-FET: A high speed power switch with low on-resistance

For high power switching applications, it is desirable to have a semiconductor device that exhibits a low on resistance during current conduction in order to minimize the steady state conduction losses, and high speed turn-off to minimize the switching losses. The ideal device must operation at high current densities during forward conduction, minimizing the chip size required for any given current handling capability and lowering costs. This article describes a new device structure which realizes these features. In this device the injection of minority carriers from the gate junction controls its admittance.     

An optimized bidirectional lightning surge protection semiconductordevice

This paper addresses the analysis of a bidirectional lightning surge protection power semiconductor device called the bidirectional breakover diode (BBD). The BBD has a high-speed response, high current capability, and low conduction and switching losses. The influence of the layout on the trigger and holding current values has been studied by means of two-dimensional (2-D) electrical simulations. The length of the peripheral N⁺ diffusion together with the location of the edge contact between the metallization and the P⁺/N⁺ diffusions are crucial in optimizing the trigger mechanism and the trigger and holding current values. The turn on of the inner cells has also been analyzed by numerical simulations, showing the effect of the central parasitic P⁺NP⁺ bipolar transistor at the initial phase of the turn on process. Experimental results have been obtained from fabricated 180-V BBD devices with holding current values in the range of 150-250 mA. The BBD surge protection capability has been corroborated by impulsive tests using a 10/1000 μs, 50 A, 1000 V, current pulse. In addition, transient losses have been monitored in order to improve the surge protection capability of the device. Finally, the static and dynamic BBD thermal behaviour has also been analyzed     

The SINFET—A Schottky injection MOS-gated power transistor

A new MOS-gated power device, the Schottky injection FET (SINFET), is described in this paper. The device offers 6 times higher current handling capability than conventional n-channel power LDMOS transistors of comparable size and voltage capability and still maintains a comparable switching speed. The low on-resistance is obtained by conductivity modulation of the high-resistivity n- drift region using a Schottky injector. Since only a small number of minority carriers are injected, the speed of the device is not degraded substantially and high latchup resistance is achieved. Breakdown voltages and specific on-resistance observed on typical devices are 170 V and 0.01 Ω . cm², respectively. Gate-turn off times are of the order of 30 ns. Two-dimensional simulation and experimental results comparing the SIN-FET with the LDMOST and lateral insulated gate transistor (LIGT) are presented.     

Effects of the doping profile on current characteristics in BSITs

Proposed are two doping profiles of the conducting channel in bipolar-mode static induction transistors (BSITs) that improve the current handling capability. By using the results obtained from two-dimensional device simulations, it is shown that BSITs with the proposed profiles exhibit higher drain current density and DC current gain than conventional BSITs. Also discussed is the tradeoff between the current and voltage capabilities     

应用NTC实现电源浪涌保护技术研究

研究应用NTC实现半导体设备电源浪涌保护技术,对电源浪涌的成因、NTC的特点及电源浪涌保护的原理进行了分析,设计了NTC电源浪涌保护电路,并通过实验展示了NTC抑制浪涌的能力与效果。