近期光刻用ArF准分子激光技术发展

193 nm ArF准分子激光光刻技术已广泛应用于90 nm以下节点半导体量产。ArF浸没式也已进入45 nm节点量产阶段。双图形光刻（DPL）技术被业界认为是下一代光刻32 nm节点最具竞争力的技术。利用双图形技术达到32 nm及以下节点已经被诸多设备制造商写入自己的技术发展线路。Cymer公司和Gigaphoton公司为双图形光刻开发了高输出功率、高能量稳定性和具有稳定的窄谱线宽度ArF准分子光源。分析了近期发展用于改进准分子激光性能的关键技术：主振-功率再生放大(MOPRA)结构、主振-功率振荡(MOPO)结构,主动光谱带宽稳定技术,先进的气体管理技术。对光刻用准分子激光光源技术发展趋势进行了简要的讨论。     

Potential applications of negative tone development in advanced lithography

Advanced lithography requires resolution enhancement techniques (customized illumination mode, litho friendly design), and alternative process flow schemes (double exposure, double patterning) in order to meet the requirements of the ITRS technology roadmap and to extend the applications of a full-field scanner with a 1.35 numerical aperture (NA) that represents the physical limit of water-based immersion ArF lithography.Today, one of the most interesting alternative processes uses the patterning inversion through a negative tone development (NTD) process step. Traditionally, the patterning (contacts or trenches) is done by using a dark field mask in combination with positive tone resist and positive tone development (PTD). By using a solvent-based developer (NTD) and a bright field mask, the same features can be transferred into a positive resist with the benefit of better image contrast and, consequently, better line width roughness (LWR) and resolution.In this work we have explored the potential applications of NTD for trenches and contact holes for the 45 nm technology node requirements and beyond. The NTD process is a promising option considering the impact on process window, LWR, CD uniformity and defectivity. The experimental result of this alternative approach to print critical dark field levels in an advanced lithography boundary has been explored.     

面向无缝拼接的并行反向光刻技术

Inverse lithography technology （ILT）, a promising resolution enhancement technology （RET） used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing methods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the parallel process. The seamless-merging-oriented parallel ILT method proposed in this paper is fast because of the parallel process; and most importantly, convergence enhancement penalty terms （CEPT） introduced in the parallel ILT optimization process take the environment into consideration as well as environmental change through target updating. This method increases the similarity of the overlapped area between guard-bands and work units, makes the merging process approach seamless and hence reduces hot-spots. The experimental results show that seamless-merging-oriented parallel ILT not only accelerates the optimization process, but also significantly improves the quality of ILT.     

浸没式光刻向22nm挺进

简述了光学光刻技术在双重图形曝光、高折射率透镜材料及浸没介质、32nm光刻现状及22nm浸没式光刻技术的进展,指出了光学光刻技术的发展趋势及进入22nm技术节点的前景。     

Thermal characterization of materials for double patterning

Among the different possibilities for sub-40 nm half-pitch devices, double patterning (DP) is one of the most promising candidates. This paper is related to the double imaging approach where the first lithographic step is followed by a resist curing to avoid any degradation of the pattern during the upper-layer resist patterning. In this paper we develop a methodology based on thermal analysis measurements to demonstrate the existence of an optimal curing temperature. The results are in good agreements with the lithographic observations showing that thermal characterization of the resist is a complementary source of information for the DP process. Moreover, we were able to provide valuable information on the evolution of the properties of the resist occurring during the curing step and some directions for next generation curing resists.     

Seamless-merging-oriented parallel inverse lithography technology

Inverse lithography technology (ILT), a promising resolution enhancement technology (RET) used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing meth-ods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the parallel process. The seamless-merging-oriented parallel ILT method proposed in this paper is fast because of the parallel process; and most importantly, convergence enhancement penalty terms (CEPT) introduced in the parallel ILT optimization process take the environment into consideration as well as environmental change through target updating. This method increases the similarity of the overlapped area between guard-bands and work units, makes the merging process approach seamless and hence reduces hot-spots. The experimental results show that seamless-merging-oriented parallel ILT not only accelerates the optimization process, but also significantly improves the quality of ILT.     

Fabrication of Ge2Sb2Te5 based PRAM device at 60 nm scale by using UV nanoimprint lithography

Phase change memory is one of the most promising non-volatile memory for the next generation memory media due to its simplicity, wide dynamic range, fast switching speed and possibly low power consumption. Low power consuming operation of phase change random access memory (PRAM) can be achieved by confining the switching volume of phase change media into nanometer scale. Nanoimprint lithography is an emerging lithographic technique in which surface protrusions of a mold such as sub-100 nm patterns are transferred into a resin layer easily. In this study, crossbar structures of phase change device array based on Ge₂Sb₂Te₅ were successfully fabricated at 60 nm scale by two consecutive UV nanoimprint lithography and metal lift-off process, which showed on/off resistance ratio up to 3000.     

A study of virtual lithography process for polymer directed self-assembly

For the feature size scaling down to tens of nanometers, the top-down approaches are getting more severe because the extremely ultra-violet (EUV) technique, the high-index fluid-based immersion ArF lithography, and the double patterning technology (DPT) under development may be cover one or two generations. An alternative technology to extend lithography patterning beyond current resolution limits is to combine the top-down lithography and bottom-up assembly.In this paper, an directed self-assembly lithography process of “bottom-up” block copolymer self-assembly, is modeled and simulated in molecular-scale. Impacts of block polymer components on pattern formation are analyzed and discussed.     

Large-area high-resolution lithography and photoablation systems for microelectronics and optoelectronics fabrication

An important requirement in the production of numerous microelectronic, optoelectronic, and microsystem devices is lithographic patterning on a large area with high image resolution and precise layer-to-layer alignment. Whereas for production of semiconductor devices advances have been steadily made in steppers and other conventional lithography systems, the lithography requirements for the fabrication of large-format products, such as displays, multilayer circuits, and flexible electronics, are distinctly different, rendering various conventional lithography tools inadequate. These requirements and distinctions of large-area lithography are discussed. In the last several years, we have developed a new class of projection lithography systems that provide both high-resolution imaging and very large exposure area capability with high-precision alignment. The systems, using excimer laser sources, function as dual-mode, high-throughput production tools, capable of patterning in photoresists as well as photoablation in polymers, making them attractive for production of numerous large-format products, with feature sizes ranging from 15 /spl mu/m to below 1 /spl mu/m and substrate sizes ranging from 150 /spl times/ 150 mm to 610 /spl times/ 915 mm. We review the new lithography system technology, several completed systems, and demonstrated results.     

Stencil-assisted reactive ion etching for micro and nano patterning

Stencil-assisted oxygen reactive ion etching is a low-cost and parallel process for the replication of micrometric and nanometric patterns in any organic material. This lithography process allows the patterning of organic material non sensitive to electronic or optical radiations, sensitive to solvents, or already patterned which cannot be patterned by conventional lithography methods. We demonstrate the versatility of stencil-assisted reactive ion etching though 3 examples. First to define 500 nm holes in PMMA. Secondly, the fabrication step has been integrated in a lift-off process of metal or molecular self-assembled monolayers. We finally apply stencil-assisted reactive ion etching to pattern an assembly of 100 nm latex nanoparticles.     

FRAM design style utilising bit-plate parallel cell architecture

A new FRAM (ferroelectric RAM) design method, utilising a bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by the on-pitch plate control circuitry. It also reduces the power consumption in the memory array. Implementation results for a 0.13 /spl mu/m CMOS technology, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of a conventional structure.     

Security Vulnerabilities: From Analysis to Detection and Masking Techniques

This paper presents a study that uses extensive analysis of real security vulnerabilities to drive the development of: 1) runtime techniques for detection/masking of security attacks and 2) formal source code analysis methods to enable identification and removal of potential security vulnerabilities. A finite-state machine (FSM) approach is employed to decompose programs into multiple elementary activities, making it possible to extract simple predicates to be ensured for security. The FSM analysis pinpoints common characteristics among a broad range of security vulnerabilities: predictable memory layout, unprotected control data, and pointer taintedness. We propose memory layout randomization and control data randomization to mask the vulnerabilities at runtime. We also propose a static analysis approach to detect potential security vulnerabilities using the notion of pointer taintedness.     

ELIAS: An Accurate and Extensible Lithography Aerial Image Simulator With Improved Numerical Algorithms

Lithography simulators have been playing an indispensable role in process optimization and design for manufacturability (DFM). The ever smaller feature sizes demand higher numerical accuracy and faster runtime on these lithography simulators. Aerial image simulation is the first key step in lithography simulation, and the method using transmission cross coefficient (TCC), which is a two-dimensional integral, is the most commonly used technique for full-chip aerial image simulation. In this paper, we present a very accurate, yet efficient and extensible aerial image simulator, ELIAS. We find that the majority of the numerical error during the TCC computation is due to the discontinuous boundaries of the support of the TCC integrand. We reduce the error dramatically by using a recursive integration algorithm. Because TCC is usually computed on uniform grids, we further speed up the algorithm without increasing the errors. Given the same accuracy, our new algorithm can speed up the runtime by $100times $– $1000times $. Our algorithm also provides smooth tradeoff between accuracy and runtime. It can be used to benchmark other lithography aerial simulators. In addition, ELIAS provides an open-source, flexible software framework to incorporate different lithography settings.      

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 μm to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFT's for load devices. The effect of the Si₃N₄ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6×10⁶ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns     

Direct Patterning of Metal Chalcogenide Semiconductor Materials

Lithography is one of the most widely used methods for cutting‐edge research and industrial applications, mainly owing to its ability to draw patterns in the micro and even nanoscale. However, the fabrication of semiconductor micro/nanostructures via conventional electron or optical lithography technologies often requires a time‐consuming multistep process and the use of expensive facilities. Herein, a low‐cost, high‐resolution, facile, and versatile direct patterning method based on metal–organic molecular precursors is reported. The ink‐based metal–organic precursors are found to operate as negative resists, with the material exposed by different methods (electron‐beam/laser/heat/ultraviolet (UV)) to render them insoluble in the development process. This technical process can deliver metal chalcogenide semiconductors with arbitrary 2D/3D patterns with sub‐50 nm resolution. Electron beam lithography, two‐photon absorption lithography, thermal scanning probe lithography, and UV photolithography are demonstrated for the direct patterning process. Different metal chalcogenide semiconductor nanodevices, such as photoconductive selenium‐doped Sb₂S₃ nanoribbons, p‐type PbS single‐nanowire field‐effect transistors, and p‐n junction CdS/Cu₂S nanowire solar cells, are fabricated by this method. This direct patterning technique is a versatile and simple micro/nanolithography technology with considerable potential for “lab‐on‐a‐chip” preparation of semiconductor devices.     

A 3.84 GIPS integrated memory array processor with 64 processingelements and a 2-Mb SRAM

An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2-Mb SRAM has been developed for image processing. The chip attains a 3.84 GIPS peak performance through the use of SIMD parallel processing and a 1.28 GByte/s on-chip processor-memory bandwidth. The IMAP is capable of parallel indirect addressing, which increases applications for parallel algorithms. Large power consumption with the wide memory bandwidth is avoided by reducing the number of active sense amplifiers and adopting dynamic power control. Fabricated with a 0.55-μm BiCMOS double layer metal process technology, the IMAP contains 11 million transistors in a 15.1×15.6 mm² die area     

NGL comparable to 193-nm lithography in cost,footprint, and power consumption

A comparison of ArF immersion single exposure, double patterning, extreme UV, and multi-e-beam maskless lithography (MEB ML2) systems, is made on their special characteristics, then in footprint, cost, and raw energy consumption. Only the MEB ML2 system has the potential to mimic ArF immersion single exposure in the three areas compared. In addition, MEB ML2 does not have the burden of mask-contributed CD and overlay variation, mask cost, cycle time, pellicle, contamination, and electrostatic-discharge-induced damage. Key challenges to develop MEB ML2 into a high-volume manufacturing technology are also given.     

45nm工艺及材料的最新动态

介绍了45nm芯片、工艺和设备的最新动态。英特尔、TI、IBM、特许、英飞凌和三星都推出了45nm功能芯片。45nm主要工艺包括光刻、应变硅、低k电介质、Cu互连、高k电介质和离子注入等。光刻工艺采用193nmArF/浸没式光刻机。45nm工艺中应变硅技术已步入第三代,它综合采用双应力衬垫、应力记忆和嵌入SiGe层。     

Spin-transfer torque RAM technology: Review and prospect

Non-volatile RAM (NV-RAM) enables instant-on/off computing, which drastically reduces power consumption. One of the most promising candidates for NV-RAM technology is the spin-transfer torque RAM (SPRAM) based on magnetic tunnel junction (MTJ) device technology. This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability. At the circuit level, a disruptive read operation for future large integration scale is described. A 4F² memory cell and a multi-bit cell approach are also presented. Finally, the potential value of instant-on/off computing through NV-RAM and its impact are explored.     

Status and trends in modern micro- and nanotechnology

The recent development from micro- to nanotechnology enables new ideas and new physical effects to be implemented in both conventional and novel devices. Examples of fast developing fields in this context are electronic, photonic and magnetic components for sensor, memory, and logic applications. Optical lithography, the traditional path of patterning, is supplemented with sophisticated methods to access the nanoworld.