Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

掺杂GaAs/Al0.3Ga0.7As超晶格的光致发光特性分析

在室温下,通过光致发光实验研究了用MBE生长的GaAs/Al0.3Ga0.7As超晶格材料的光致发光特性,对测得的发光峰进行了指认.理论计算和实验结果符合很好.     

Photoluminescence studies of In0.7Al0.3As/In0.75Ga0.25As/In0.7Al0.3As metamorphic heterostructures on GaAs substrates

The influence of the design of the metamorphic buffer of In_0.7Al_0.3As/In_0.75Ga_0.25As metamorphic nanoheterostructures for high-electron-mobility transistors (HEMTs) on their electrical parameters and photoluminescence properties is studied experimentally. The heterostructures are grown by molecular-beam epitaxy on GaAs (100) substrates with linear or step-graded In _x Al_{1 ? x} As metamorphic buffers. For the samples with a linear metamorphic buffer, strain-compensated superlattices or inverse steps are incorporated into the buffer. At photon energies ?ω in the range 0.6–0.8 eV, the photoluminescence spectra of all of the samples are identical and correspond to transitions from the first and second electron subbands to the heavy-hole band in the In_0.75Ga_0.25As/In_0.7Al_0.3As quantum well. It is found that the full width at half-maximum of the corresponding peak is proportional to the two-dimensional electron concentration and the luminescence intensity increases with increasing Hall mobility in the heterostructures. At photon energies ?ω in the range 0.8–1.3 eV corresponding to the recombination of charge carriers in the InAlAs barrier region, some features are observed in the photoluminescence spectra. These features are due to the difference between the indium profiles in the smoothing and lower barrier layers of the samples. In turn, the difference arises from the different designs of the metamorphic buffer.     

Si基HgCdTe变面积光伏探测器的变温特性研究

通过变面积Si基HgCdTe器件变温I-V测试和暗电流特性拟合分析,研究了不同偏压下n-on-p型Si基HgCdTe光伏器件的暗电流成分与Si基HgCdTe材料少子扩散长度和少子寿命随温度的变化规律.在液氮温度下,随着反向偏压的增大器件的表面漏电流在暗电流中所占比重逐渐增加.在零偏压下,当温度低于200 K时材料的少子...     

High uniformity of Al0.3Ga0.7As/ln0.15Ga0.85As doped-channel structures grown by molecular beam epitaxy on 3″ GaAs substrates

Al_0.3Ga_0.7As/ln_0.15Ga_0.85As doped-channel structures were grown by molecular beam epitaxy on 3″ GaAs substrates. The uniformities of electrical and optical properties across a 3″ wafer were evaluated. A maximum 10% variation of sheet charge density and Hall mobility was achieved for this doped-channel structure. A1 μm long gate field-effect transistor (FET) built on this layer demonstrated a peak transconductance of 350 mS/mm with a current density of 470 mA/mm. Compared to the high electron mobility transistors, this doped-channel FET provides a higher current density and higher breakdown voltage, which is very suitable for high-power microwave device applications.     

Persistent photo-conductance and photoquenching of selectively doped Al0.3Ga0.7As GaAs/heterojunctions

The dependence on photon energy of the persistent photoconductivity (PPC) in selectively doped high mobility Al_0.3Ga_0.7As—GaAs heterostructures has been measured at temperatures below 80 K. A decrease in conductivity due to light exposure at one wavelength after exposure to light at another wavelength — photo-quenching — is also found. It is concluded that deep centers in GaAs and AlGaAs other than the DX center in AlGaAs are mainly responsible for PPC.     

溅射ZnO薄膜钝化GaAs表面性能的研究

为了改善GaAs(110)与自身 氧化物界面由于高表面态密度而引起的费米能级钉扎(pinning)问题 ,提出采用射频磁控溅射技 术在GaAs(110)衬底上沉积一定厚度 ZnO薄膜作为钝化层,并利用光 致发光(PL)光谱和X射线光电子能谱(XPS) 等方法对ZnO薄膜的光学特性及钝化性能进行表征。实验结果表明,经ZnO薄膜钝化后的 GaAs样品,其本征PL峰强度提高112.5%,杂质峰强度下降82.4%。XPS光谱分析表明,Ga和As原子的比值从1.47降低 到0.94,ZnO钝化层能 够抑制Ga和As的氧化物形成。因此,在GaAs表面沉积ZnO薄膜是一种可行的GaAs表面钝化 方法。     

Investigation of DX centers in modulation-doped field-effect transistor-type Al0.3Ga0.7As/GaAs heterostructures using a fourier-transform deep level transient spectroscopy system

Al_0.3Ga_0.7As:Si/GaAs modulation-doped field-effect transistor-type heterostructures were grown using two different growth temperatures (500 and 620°C) and three doping modes (δ-doping, pulse-doping, and uniform-doping). Deep level transient spectroscopy (DLTS) measurements were performed on these structures using a new Fourier-analysis method. Up to four DLTS peaks, related to the different possible configurations of the nearest Al and Ga neighbors around each DX site, were observed. Both the growth temperature and the doping-mode are found to affect the DLTS spectra, in particular the number of observed peaks and their width. These results are interpreted in terms of the different mobilities of the Si doping atoms on the surface during growth.     

Study of grown-in defects and effect of thermal annealing in Al0.3Ga0.7As and GaAs LPE layers

Studies of the grown-in deep-level defects in the undoped n-Al_xGa_1-xAs (x = 0.3) and GaAs epitaxial layers prepared by the liquid phase epitaxy (LPE) techniques have been made, using DLTS, I-V and C-V measurements. The effect of 300 °C thermal annealing on the grown-in defects was investigated as a function of annealing time. The results showed that significant reduction in these grown-in defects can be achieved via low temperature thermal annealing process. The main electron and hole traps observed in the Al_0.3Ga_0.7As LPE layer were due to the E_c-0.31 eV and E_v+0.18 eV level, respectively, while for the GaAs LPE layer, the electron traps were due to the E_c-0.42 and 0.60 eV levels, and the hole traps were due to E_v+0.40 and 0.71 eV levels. Research supported in part by the Air Force Wright Aeronautical Laboratories, Aeropropulsion Lab., Wright Patterson Air Force Base, Ohio, subcontract through SCEEE, contract F33615-81-C-2011, task-4, and in part by AFOSR grant no. 81-0187.     

不同缓冲层对GaAs基In_(0.3)Ga_(0.7)As材料特性的影响

采用组分跳变和低温大失配缓冲层技术在GaAs衬底上外延了In0.3Ga0.7As材料。测试结果表明,采用组分跳变缓冲层生长的In0.3Ga0.7As主要依靠逐层间产生失配位错来释放应力,并导致表面形成纵横交错的Cross-hatch形貌;而采用低温大失配缓冲层技术则主要通过在低温缓冲层中形成大量缺陷来充分释放应力,并在后续外延的In0.3Ga0.7As表面没有与失配位错相关的Cross-hatch形貌出现。此外,仅需50nm厚的低温大失配缓冲层即可促使In0.3Ga0.7As中的应力完全释放,这种超薄缓冲层技术在工业批产中显得更为经济。     

Effect of GaAs (100) substrate misorientation on the electrical parameters and surface morphology of metamorphic In0.7Al0.3As/In0.75Ga0.25As/In0.7Al0.3As HEMT nanoheterostructures

The results of studies of the effect of GaAs (100) substrate misorientation on the electrical parameters and surface morphology of high electron mobility In_0.7Al_0.3As/In_0.75Ga_0.25As/In_0.7Al_0.3As/GaAs nanoheterostructures are reported. Using molecular-beam epitaxy, two identical structures with a stepped compositional profile of the metamorphic In _x Al_{1 ? x} As (Δ _x = 0.05) buffer are grown on substrates of two types: a singular GaAs substrate with the orientation (100) ± 0.5° and a GaAs (100) substrate misoriented by (2 ± 0.5)° in the $\left[ {0\bar 1\bar 1} \right]$ direction. It is found that, in the case of the misoriented substrate, the concentration of the two-dimensional electron gas is ～40% higher. Broadening of the photoluminescence spectra and a shift of the peaks to lower photon energies, as experimentally observed in the case of the misoriented substrate, are attributed to the increased roughness of the heterointerfaces and strengthened fluctuations of the quantum-well width.     

Cleaning and passivation of the Si(100) surface by low temperature remote hydrogen plasma treatment for Si epitaxy

This paper presents the results of a study of the hydrogen-passivated Si(100) surface prepared by a remote hydrogen plasma treatment which serves the dual purpose of cleaning and passivating the Si(100) surface prior to low temperature Si epitaxy by Remote Plasma-enhanced Chemical Vapor Deposition (RPCVD). The remote hydrogen plasma treatment was optimized for the purposes of cleaning and passivation, respectively. To achieve a clean, defect-free substrate surface, the remote hydrogen plasma process was first optimized using Transmission Electron Microscopy (TEM) and Auger Electron Spectroscopy (AES). For hydrogen passivation, the substrate temperature was varied from room temperature to 250° C in order to investigate the degree of passivation as a function of substrate temperature by examining the amount of oxygen readsorbed on the substrate surface after air exposure. Low temperature Si expitaxy was subsequently performed on the air-exposed substrates without further cleaning to evaluate the effectiveness of the hydrogen passivation. It was found that better Si surface passivation is achieved at lower substrate temperatures as evidenced by the fact that less oxygen is observed on the surface using AES and Secondary Ion Mass Spectroscopy (SIMS) analyses. The amount of readsorbed oxygen on the H-passivated Si surface after a two hour air exposure was found to be as low as 0.1 monolayer from SIMS analysis. Using Reflection High Energy Electron Diffraction (RHEED) analysis, different surface reconstructions ((3 × 1) and (1 × 1)) were observed for H-passivated Si surfaces passivated at various temperatures, which was correlated to the results of AES and SIMS analyses. Epitaxial growth of Si films at 305° C was achieved on the air-exposed Si substrates, indicating a chemically inert Si surface as a result of hydrogen passivation. A novel electron-beam-induced-oxygen-adsorptiom phenomena was observed on the Hpassivated Si surface. Scanning Auger Microscopy (SAM) analysis was performed to study the reaction kinetics as well as the nature of Si—H bonds on the H-passivated Si surface. Preliminary results show that there is a two-step mechanism involved, and oxygen adsorption on the H-passivated Si surface due to electron beam irradiation may be due to the formation of O-H groups rather than the creation of Si—O bonds.     

Low threading dislocation density GaAs on Si(100) with InGaAs/GaAs strained-layer superlattice grown by migration-enhanced epitaxy

This paper reports a promising approach for reducing the density of threading dislocations in GaAs on Si. In _x Ga_1-x As/GaAs strained-layer superlattices (SLSs) grown by migration-enhanced epitaxy at 300° C on GaAs/Si acted as barriers to threading dislocations. Unlike conventional high-temperature-grown SLSs, the low-temperature-grown SLSs were hardly relaxed by the formation of misfit dislocations at GaAs/SLS interfaces, and this allowed them to accumulate considerable strain. New threading dislocation generation due to the misfit dislocation was also suppressed. These factors caused effective bending of threading dislocations and significantly reduced the dislocation density. For the samples that had an SLS withx = 0.3, the average etch-pit density was 7 × 10⁴ cm^-2, which is comparable to that of GaAs substrates.     

Large area depositon of Cd1-xZnxTe on GaAs and Si substrates by metalorganic chemical vapor deposition

Results of large-area (up to 1000 cm²/run) Cd_1-xZn_xTe heteroepitaxy on both GaAs and GaAs/Si substrates by metalorganic chemical vapor deposition (MOCVD) are presented. Cd_1-xZn_xTe (x = 0-0.1) films exhibited specular surface morphology, 1% thickness uniformity (standard deviation), and compositional uniformity (Δx) of ±0.002 over 100 mm diam substrates. For selected substrate orientations and deposition conditions, the only planar defects exhibited by (lll)B Cd_1-xZn_xTe/GaAs/Si films were lamella twins parallel to the CdTe/GaAs interface; these do not propagate through either the Cd_1-xZn_xTe layer or subsequently deposited liquid phase epitaxy (LPE) HgCdTe layer(s). Background Ga and As-impurity levels for Cd_1-xZn_xTe on GaAs/Si substrates were below the secondary ion mass spectroscopy detection limit. Preliminary results of HgCdTe liquid phase epitaxy using a Te-rich melt on Si-based substrates resulted in x-ray rocking curve linewidths as narrow as 72 arc-sec and etch-pit densities in the range 1 to 3 x 10⁶ cm².     

A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).     

硅衬底上GaAlAs/GaAs单量子阱激光器

采用MOCVD方法在硅衬底上生长了带应力超晶格的GaAlAs/GaAs单量子阱外延片,并用质子轰击隔离法制成10微米条形单量子阱激光器.在室温下加脉冲电流(重复频率26KHz,脉宽1μs)观察到受激发射.最低阈电流92mA、激射波长849.2nm,外微分量子效率11％.     

Capacitance-Voltage characteristics of metal-insulator-semiconductor diodes with S passivation and Si interface control layers on GaAs and InP

GaAs and InP surfaces have been prepared by gas-phase and liquid-phase polysulfide passivation techniques followed by the deposition of Si interface control layers (ICLs) by e-beam evaporation. For GaAs surfaces, the performance of an ICL consisting of 1.5 nm Si on top of 0.5 nm of Ge has also been evaluated. Metal-insulator-semiconductor diodes with aluminum top electrodes were fabricated on these surfaces using silicon nitride deposited by a remote plasma-enhanced chemical vapor technique or silicon dioxide deposited by a conventional direct plasma-enhanced chemical vapor deposition technique. The quality of the interfaces was analyzed by capacitance-voltage (C-V) measurements and the interface state densities D_it were deduced from the C-V data using the high-low method. Values as low as 1.5 × 10¹² eV⁻¹cm⁻² were obtained for polysulfide-passivated GaAs surfaces with a Ge-Si or Si ICL, the lowest ever demonstrated using the high-low method for an ex-situ technique not involving GaAs epitaxy. For InP, the Si ICL does not reduce D_it below that of 2 × 10¹² eV⁻¹ cm ⁻² that was obtained for the polysulfide passivated surface. The Si ICL produces an interface that degrades more slowly on exposure to air for both GaAs and InP.     

Influence of Ga vs As prelayers on GaAs/Ge growth morphology

The surface morphology of GaAs films grown on Ge substrates is studied by scanning force microscopy. We find a dramatic difference arising from Ga as opposed to As prelayers in the formation of anti-phase boundaries (APBs), surface features near threading dislocations, and surface roughness, for films as thick as 1 μm. Ga prelayer samples are smooth; thin films display some APBs with predominantly one growth domain while the 1 μm thick film displays the morphology of a homoepitaxial GaAs film. In contrast, As prelayer samples are rough with complicated APB structures, which can be attributed to the increase in single steps during As₂ deposition.     

Effects of high temperature annealing on the device characteristics of Ga0.52In0.48P/GaAs and Al0.52In0.48P/GaAs heterojunction bipolar transistors

GaInP/GaAs and AlInP/GaAs heterojunction bipolar transistor (HBT) structures were grown by low pressure metalorganic vapor phase epitaxy and annealed at various temperatures up to 675°C for 15 min. Subsequent comparisons with HBTs fabricated on both annealed and unannealed control samples showed no effects for annealing up to and including 575°C, but significant changes in the electrical characteristics were observed at an annealing temperature of 675°C. For the GaInP/GaAs devices, the base current increased by a significant amount, reducing the gain and increasing the base current ideality factor from 1.07 to 1.9. Photoluminescence and electrical measurements on the structures indicated that both the emitter and base were affected by an increase in the recombination times in those regions. These effects were attributed to an out-diffusion of hydrogen from the base during annealing. The emitter of the AlInP/GaAs HBT was affected less by the hydrogen diffusion because of the larger bandgap. These observations have important implications for device performance dependence on the details of the temperature/time profile subsequent to the base growth.