共查询到20条相似文献,搜索用时 0 毫秒
1.
We present here an analysis and simulation model of an unconstrained on-off poppet valve, which includes the modeling of a piezoelectric actuator (PEA), Hertzian contact, dynamics of poppet motion, and airflow through an orifice. The flow rate generated and the input/output relationship between input frequency/flow rate and voltage/flow rate at different levels of inlet pressure were measured experimentally. Simulation models were built and verified experimentally for valves with different piezoelectric dimensions. Comparisons of simulation and experimental results showed good agreement, thus validating the proposed dynamic analysis. This model can therefore be used to understand the behavior of unconstrained on-off poppet valves. Poppet size did not have a significant effect on flow rate output. Also, the flow rate responses of different sizes of PEAs revealed that larger cross-sectional areas produced higher flow rates. Based on the experimental and simulation results, unconstrained valves were characterized as on-off valves. These findings indicate that this analytical model can be used to predict or estimate the input/output behavior of valves with different parameters. 相似文献
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《Electron Device Letters, IEEE》2009,30(7):766-768
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Jing Xu Xinliang Zhang Jianji Dong Deming Liu Dexiu Huang 《Photonics Technology Letters, IEEE》2008,20(8):596-598
A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate. 相似文献
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Jian Wang Junqiang Sun Qizhen Sun 《Photonics Technology Letters, IEEE》2007,19(8):541-543
All-optical logic gate based on parametric processes in periodically poled lithium niobate (PPLN) waveguides is a promising technique in future high-speed all-optical signal processing. A simple realization of switchable or/xor logic gates at 40 Gb/s is proposed and numerically demonstrated using sum-frequency generation in a PPLN waveguide. By appropriately adjusting the input signal power and choosing the waveguide length, or and xor logic gates can be obtained. The operation performance is simulated, including eye diagrams and Q-factor. The input signal powers and waveguide length are optimized, providing a theoretical basis for achieving the optimal performance for the switchable or/xor logic gates 相似文献
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Jian Chen Bing Xie Yong Liang Guan Yixin Wang 《Photonics Technology Letters, IEEE》2007,19(20):1592-1594
An ON-OFF-keying optical receiver with dual thresholds and an erasure zone is proposed. This configuration can be applied to track the optimized decision level adaptively and obtain additional coding gain from forward-error correction without increasing the code rate. Our analysis shows that in both unamplified and optically preamplified receivers, the required Q value for the bit-error rate of 10-12 can be reduced by 1.8 dB, if errors arise in burst nature and the optimized erasure zone width is around 7%-11% of the signal swing. 相似文献
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Saito W. Nitta T. Kakiuchi Y. Saito Y. Tsuda K. Omura I. Yamaguchi M. 《Electron Device Letters, IEEE》2007,28(8):676-678
The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device. 相似文献
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《Photonics Technology Letters, IEEE》2008,20(3):211-213
All-optical flexible 20-Gb/s logic and gate based on cascaded sum- and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated. The theoretical analyses further indicate that 40-, 80-, and 160-Gb/s ultrahigh-speed logic and operations can potentially be performed. Moreover, it is expected that the and output can be tuned in a wide wavelength range (67 nm) with slight fluctuation of the Q-factor and extinction ratio. 相似文献
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Larcher L. Padovani A. Pavan P. Fantini P. Calderoni A. Mauri A. Benvenuti A. 《Electron Device Letters, IEEE》2008,29(10):1152-1154
In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications. 相似文献
11.
Varghese D. Kufluoglu H. Reddy V. Shichijo H. Mosher D. Krishnan S. Muhammad Ashraful Alam 《Electron Devices, IEEE Transactions on》2007,54(10):2669-2678
Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds. 相似文献
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《Photonics Technology Letters, IEEE》2009,21(7):411-413
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《Electron Device Letters, IEEE》2009,30(1):30-32
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In this paper, a lognormal approximation is proposed for the sum of lognormal processes weighted by binary processes. The analytical approach moves from the method early proposed by Wilkinson for approximating first-order statistics of a sum of lognormal components, and extends to incorporate second-order statistics and the presence of both time-correlated random binary weights and cross-correlated lognormal components in moments' matching. Since the sum of weighted lognormal processes models the signal-to-interference-plus-noise ratio (SINR) of wireless systems, the method can be applied to evaluate in an effective and accurate way the outage occurrence rate and outage duration for different wireless systems of practical interest. In a frequency-reuse-based cellular system, the method is applied for various propagation scenarios, characterized by different shadowing correlation decay distances and correlations among shadowing components. A further case of relevant interest is related to power-controlled wideband wireless systems, where the random weights are binary random variables denoting the activity status of each interfering source. Finally, simulation results are used to confirm the validity of the analysis. 相似文献
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《Electron Device Letters, IEEE》2009,30(7):769-771
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《Solid-State Circuits, IEEE Journal of》2008,43(12):2706-2715
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Muller C.R. Worschech L. Hopfner P. Hofling S. Forchel A. 《Electron Device Letters, IEEE》2007,28(10):859-861
Room-temperature operation of a logic NOR gate is demonstrated. The NOR gate is based on three three-terminal junctions (TTJs) monolithically integrated in a modulation-doped GaAs/AlGaAs heterostructure without any external load resistance. For the logic NOR gate, one of the TTJs serves as load transistor, whereas the other two are used as inputs. Each TTJ has a 90-nm-wide channel and shows clear transistor characteristics with drain currents up to 10 muA for a drain voltage of 1 V. Furthermore, voltage amplification is demonstrated for the logic NOR-gate function. 相似文献
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《Electron Device Letters, IEEE》2009,30(9):898-900
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