Miniaturized Unconstrained on– off Pneumatic Poppet Valve—Experiment and Simulation

We present here an analysis and simulation model of an unconstrained on-off poppet valve, which includes the modeling of a piezoelectric actuator (PEA), Hertzian contact, dynamics of poppet motion, and airflow through an orifice. The flow rate generated and the input/output relationship between input frequency/flow rate and voltage/flow rate at different levels of inlet pressure were measured experimentally. Simulation models were built and verified experimentally for valves with different piezoelectric dimensions. Comparisons of simulation and experimental results showed good agreement, thus validating the proposed dynamic analysis. This model can therefore be used to understand the behavior of unconstrained on-off poppet valves. Poppet size did not have a significant effect on flow rate output. Also, the flow rate responses of different sizes of PEAs revealed that larger cross-sectional areas produced higher flow rates. Based on the experimental and simulation results, unconstrained valves were characterized as on-off valves. These findings indicate that this analytical model can be used to predict or estimate the input/output behavior of valves with different parameters.     

Room Temperature Single-Electron Transistor Featuring Gate-Enhanced on -State Current

A single-electron transistor operating at room temperature was successfully fabricated by an improved nanodamascene process. It consists in a gated titanium nanowire interspersed by two very closely spaced tunnel junctions constituting a Coulomb island. The improvement in the process concerns the presence of an individual control gate close to the island, paving the way toward the fabrication of single-electron circuits. Moreover, a final oxidizing plasma treatment was used to tune the tunnel junction capacitances and, thus, the device operating temperature. As expected, electrical characteristics showed Coulomb blockade at room temperature, with an unexpectedly high on-state current.      

Simultaneous All-Optical and and nor Gates for NRZ Differential Phase-Shift-Keying Signals

A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate.     

Proposal for All-Optical Switchable or/xor Logic Gates Using Sum-Frequency Generation

All-optical logic gate based on parametric processes in periodically poled lithium niobate (PPLN) waveguides is a promising technique in future high-speed all-optical signal processing. A simple realization of switchable or/xor logic gates at 40 Gb/s is proposed and numerically demonstrated using sum-frequency generation in a PPLN waveguide. By appropriately adjusting the input signal power and choosing the waveguide length, or and xor logic gates can be obtained. The operation performance is simulated, including eye diagrams and Q-factor. The input signal powers and waveguide length are optimized, providing a theoretical basis for achieving the optimal performance for the switchable or/xor logic gates     

An on–off-Keying Optical Receiver With Dual Thresholds and Erasure Zone

An ON-OFF-keying optical receiver with dual thresholds and an erasure zone is proposed. This configuration can be applied to track the optimized decision level adaptively and obtain additional coding gain from forward-error correction without increasing the code rate. Our analysis shows that in both unamplified and optically preamplified receivers, the required Q value for the bit-error rate of 10^-12 can be reduced by 1.8 dB, if errors arise in burst nature and the optimized erasure zone width is around 7%-11% of the signal swing.     

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.     

PPLN-Based Flexible Optical Logic and Gate

All-optical flexible 20-Gb/s logic and gate based on cascaded sum- and difference-frequency generation in a periodically poled lithium niobate waveguide is proposed and experimentally demonstrated. The theoretical analyses further indicate that 40-, 80-, and 160-Gb/s ultrahigh-speed logic and operations can potentially be performed. Moreover, it is expected that the and output can be tuned in a wide wavelength range (67 nm) with slight fluctuation of the Q-factor and extinction ratio.     

Modeling nand Flash Memories for IC Design

In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling effects which will become extremely important in future technology generations. This model is a very valuable tool for IC designers to optimize NVM circuits, particularly in multilevel applications.     

off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.     

Optical Encryption With OCDMA Code Swapping Using All-Optical xor Logic Gate

A novel optical code-division multiple access (OCDMA) transmission system with all-optical exclusive or (xor) encryption architecture is proposed and demonstrated. This all-optical system conducts OCDMA code swapping based on xor operation. This multilayer approach eliminates radio-frequency data radiation and improves the confidentiality of the transmission system.      

Dual Gate ZnO-Based Thin-Film Transistors Operating at 5 V: nor Gate Application

We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick $hbox{Al}_{2}hbox{O}_{3}$ for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 $^{ circ}hbox{C}$. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 $ hbox{cm}^{2}/hbox{V} cdot hbox{s}$, a high saturation current of 6 $muhbox{A}$, and an on/off current ratio of $sim hbox{10}^{6}$, while SG- and GP-mode TFTs showed a similar value of mobility but with lower current. Using DG and GP modes, nor gate operation was well demonstrated.      

Approximation for a Sum of on-off Lognormal Processes With Wireless Applications

In this paper, a lognormal approximation is proposed for the sum of lognormal processes weighted by binary processes. The analytical approach moves from the method early proposed by Wilkinson for approximating first-order statistics of a sum of lognormal components, and extends to incorporate second-order statistics and the presence of both time-correlated random binary weights and cross-correlated lognormal components in moments' matching. Since the sum of weighted lognormal processes models the signal-to-interference-plus-noise ratio (SINR) of wireless systems, the method can be applied to evaluate in an effective and accurate way the outage occurrence rate and outage duration for different wireless systems of practical interest. In a frequency-reuse-based cellular system, the method is applied for various propagation scenarios, characterized by different shadowing correlation decay distances and correlations among shadowing components. A further case of relevant interest is related to power-controlled wideband wireless systems, where the random weights are binary random variables denoting the activity status of each interfering source. Finally, simulation results are used to confirm the validity of the analysis.     

Investigation of the Electron-Injection Spread in Barrier-Engineered NAND Flash Memories

This letter investigates the threshold voltage statistical spread induced by the electron-injection process during programming of barrier-engineered floating-gate nand Flash memories. The spread is shown to be independent of the tunnel-dielectric stack composition for low amplitudes of the programming staircase, for which the granular electron injection follows the Poisson statistics. Differences in the spread arise instead for large staircase step amplitudes, as in this regime the sub-Poissonian nature of the electron-injection process strictly depends on the steepness of the tunnel-dielectric current–voltage characteristics. This steepness can be modified by changing the electron-injection regime from Fowler–Nordheim (FN) to direct tunneling (DT) to modified FN (MFN): MFN is shown to allow a reduction of the electron-injection spread with respect to FN tunneling, while the DT regime gives rise to a large increase of the spread.      

The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves $> ,$18 dB conversion gain, a flat noise figure $≪, $5.5 dB from 500 MHz to 7 GHz, IIP2$ ={+}$20 dBm and IIP3 $={-}$3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than ${hbox{0.01~mm}}^{2}$ in 65 nm CMOS.      

Monolithically Integrated Logic nor Gate Based on GaAs/AlGaAs Three-Terminal Junctions

Room-temperature operation of a logic NOR gate is demonstrated. The NOR gate is based on three three-terminal junctions (TTJs) monolithically integrated in a modulation-doped GaAs/AlGaAs heterostructure without any external load resistance. For the logic NOR gate, one of the TTJs serves as load transistor, whereas the other two are used as inputs. Each TTJ has a 90-nm-wide channel and shows clear transistor characteristics with drain currents up to 10 muA for a drain voltage of 1 V. Furthermore, voltage amplification is demonstrated for the logic NOR-gate function.     

Integrated Hydrogen-Sensing Amplifier With GaAs Schottky-Type Diode and InGaP–GaAs Heterojunction Bipolar Transistor

New hydrogen-sensing amplifiers are fabricated by integrating a GaAs Schottky-type hydrogen sensor and an InGaP–GaAs heterojunction bipolar transistor. Sensing collector currents ( $I_{rm CN}$ and $I_{rm CH}$) reflecting to $hbox{N}_{2}$ and hydrogen-containing gases are employed as output signals in common-emitter characteristics. Gummel-plot sensing characteristics with testing gases as inputs show a high sensing-collector-current gain $(I_{rm CH}/I_{rm CN})$ of $≫hbox{3000}$. When operating in standby mode for in situ long-term detection, power consumption is smaller than 0.4 $muhbox{W}$. Furthermore, the room-temperature response time is 85 s for the integrated hydrogen-sensing amplifier fabricated with a bipolar-type structure.