Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Controlling the delay and the transition time of the clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (V _DD), temperature, and gate oxide thickness (t _ox) on the delay and the transition time of the clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the clock signal are demonstrated.     

Exponentially tapered transmission line model of the arterialsystem

The arterial systemic tree is intricate and complex due to its numerous branches, nonuniform cross section and elasticity, and the rich harmonic composition of its pressure- and flow-pulses. To deal with this complexity, the modeling of the arterial system based on the technique of nonuniform transmission lines was undertaken. The main advantages of the technique are that it maintains a satisfactory response over a wide range of frequencies and that it analyzes the impedance and local reflection factor of various segments. The model, which utilizes far fewer parameters than previous models, supplies important information about reflections at bifurcations and impedance matching at the termination line     

Simultaneous switching noise reduction by resonant clock distribution networks

Resonant clock distribution networks are known as low-power alternatives for conventional power-hungry buffer-driven clock networks. In this paper, we investigate the simultaneous switching noise (SSN) in a resonant clock network compared to that in conventional clocking. Analytical and simulation results show that employing the clock generated by a resonant clock network reduces the SSN voltage on power supply rails. The main drawback of using a sinusoidal clock is that the short-circuit power increases in the clocked devices. This problem is also investigated and discussed analytically.     

Performance aspects of reference clock distribution for evolvingdigital networks

Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT     

Electrical and optical clock distribution networks for gigascale microprocessors

A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock distribution networks corresponding to three microprocessor families are summarized. It is found that global clock interconnect performance and short-term jitter present the greatest challenges to the continued use of conventional clock distribution methodologies. An extrapolation of trends describing the percentage of clock period consumed by global skew and short-term jitter identifies the 32-nm technology generation of the 2002 International Technology Roadmap for Semiconductors (ITRS) as the first technology generation within which alternate methods of clock distribution may be warranted. Research efforts investigating interboard through intrachip optical clock distribution are also summarized. An optical distribution network compatible with high volume manufacturing in conjunction with a suitable means of providing optical-to-electrical signal conversion comprise the two fundamental challenges facing successful implementation of an optical clock distribution network. It is found that a global guided-wave distribution capable of efficient input and output coupling of optical power is required to meet the first challenge. The identification of a suitable means of optical-to-electrical conversion, however, remains an active topic of research.     

Modeling and characterization of thermally induced skew on clock distribution networks of nanometric ICs

Temperature has traditionally been a key parameter to take into account during the many stages of IC design flows, and in particular, during the sign-off phases of critical circuit components like the Clock Distribution Networks (CDNs). While for old technologies this task was accomplished by means of worst case corner-based static analysis, the advent of nanometric CMOS technologies made this approach intrinsically inadequate.     

Novel PLL-based clock distribution scheme

A technique for minimising clock skew in VLSI chips and multichip modules is proposed. A phase-locked loop is used to tune the delay of the clock interconnects. Negative, zero and positive delays can be achieved. This allows for clock synchronisation between individual modules with locally optimised clock distribution to minimise global clock-skew.<>     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

CMOS optoelectronic components for clock distribution

Optoelectronic components for clock distribution that are fully compatible with all standard CMOS processes are described. Waveguide cores are silicon nitride, while the waveguide cladding is silicon dioxide. Polysilicon photodetectors offer responsivities up to 1.3 A/W, 10-90% rise time of 0.58 ns, and full-width half-max duration of 0.85 ns. Power budget calculations indicate that 1 μA of photocurrent from the end node detectors can be achieved with only 48 μW of optical power input into a 16-node H-tree.     

A clock distribution network for microprocessors

A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured     

Ad hoc网络时钟同步研究

由于ad hoc网络应用环境的多样性且不同的应用具有不同的同步要求，没有一种时钟同步协议可以适应各种情况。在分析了网络时钟同步困难的基础上，结合不同的ad hoc网络应用，探讨了不同应用环境下时钟同步协议的特殊性，并介绍了现有典型的ad hoc网络时钟同步协议。最后，针对ad hoc网络时钟同步中值得进一步研究的几个问题做了初步的分析。     

Coupled electro-thermal modeling and optimization of clock networks

In this paper a coupled electro-thermal model is used for the optimal design of the clock distribution tree of a high performance microprocessor. Such approach allows simultaneously to take into account both thermal and electrical constraints. In particular timing issues such as clock delay from the root of the tree to the leaves and skew between the leaves are optimized by a suitable wire and buffer sizing. At the same time the lifetime constraints of clock wires that are affected by the electromigration, enhanced by the high temperature reached in interconnects due to the Joule self-heating, are checked and respected.     

面向片上光互连的无源H树网络设计

传统的片上电互连已无法满足多核处理系统日益 增长的通信需求,在延迟、能耗和 带宽方面更具优势的片上光互连逐渐引起关注。为了降低片上光网络(optical network-on-chip,ONoC)硬件开销和提升光网络 性能,本文提出一种基于微环谐振器的16端口无源H树光互连网络。利用宽带微环谐振器设 计4组转向光路由器,降低微环谐振器使用并完成端口选择,将信号传输到8端口接收光路由 器以及3级和4级光开关来满足信号的无争用传输。实验结果表明,在16×16阵列规模下与 Crossbar、λ-Router、GWOR、LACE、Light等无源网络结 构相比,无源光H树网络仅需使用 72个微环谐振器。网络平均插入损耗1.49 dB,与λ-Router、GWOR 、TAONoC相比分别降低 了21.5%、10.7%、59.7 %,各路径平均信噪比 为17.48 dB,与λ-Router、GWOR、Light相比分别提高了38.5%、36.0%、17.1%。     

Optical broadcast and clock distribution for multi-chip-modules

In this letter, we report a new architecture for clock and broadcast distribution using optical interconnect components, such as vertical cavity surface emitting lasers (VCSEL) and pin photodiodes with benefits of diffractive optical elements (DOE) fan-out. A two-bit-large bus for broadcast or clock distribution demonstration is presented using collective wiring technologies and MCM hybridization process in a standard BGA package. Diffractive optical elements allow one to four distribution scene through an optical plate. Specific laser drivers for VCSELs and photodiode receiver are realized in complete CMOS 0.6 μm transmitter and receiver chips.     

一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

Two-photon absorption for optical clock recovery in OTDM networks

The authors describe the design and performance of an ultrafast optical clock recovery system that is based on two-photon absorption (TPA) in a silicon avalanche photodiode. Unlike many other optical clock recovery techniques, the system is shown to be polarization insensitive, broadband, low jitter, and scalable to high data rates. Moreover, the system is simple, economical, and suitable for integration with silicon electronics. Successful operation of the system is reported for speeds up to 80 Gb/s and transmission distances up to 840 km using a recirculating loop. The authors introduce a new dithering detection scheme that dramatically improves the dynamic range and decreases polarization and wavelength dependence, without introducing an additional timing jitter. The system achieves a dynamic range of 10 dB and optical bandwidth exceeding 35 nm.     

Multi-phase correlator-based realistic clock synchronization for IEEE 802.15.4 networks

Clock synchronization is one of the most crucial and fundamental issues in distributed networks. Inaccurate factors in synchronizing clocks between nodes in the network can occur at any point in the network layers. Most uncertainties caused at the upper layers can be eliminated by hardware-assisted time stamping. However, eliminating the uncertainty of a physical layer is difficult. This paper proposes a multi-phase correlator-based clock synchronization method to mitigate the time representation error at the physical layer and improve synchronization accuracy by introducing a time representation error, which is one of physical uncertainties. Further, to apply the proposed method to a realistic environment, we implement and evaluate the proposed multi-phase correlator. Our experimental results show that the accuracy of the proposed method is better than that of a conventional approach in terms of minimizing the time representation error.     

A buffer distribution algorithm for high-performance clock netoptimization

We propose a new approach for optimizing clock trees, especially for high-speed circuits. Our approach provides a useful guideline to a designer, by user-specified parameters, and three of these tradeoffs are provided in this paper. (1) First, to provide a “good” tradeoff between skew and wire length, a new clock tree routing scheme is proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and minimum rectilinear Steiner tree. Our experiments complement the theoretical results. (2) For high-speed clock distribution in the transmission line mode (e.g., multichip modules) where interconnection delay dominates the clock delay, buffer congestion might exist in a layout. Using many buffers in a small wiring area results in substantial interline crosstalks as well as wirability, when the elongation of the imbalanced subtrees is necessary. Placing buffers evenly (locally or globally) over the plane at the minimum impact on wire length increase helps avoid buffer congestion and results in less crosstalk between clock wires. Thus, an effective technique for buffer distribution is proposed. Experimental results verify the effectiveness of the proposed algorithms. (3) Finally, a postprocessing step constraining on phase-delay is also proposed. The technique is based on a combination of hierarchical bottom-up geometric matching and bounded radius minimum spanning tree. The proposed algorithm has an important application in MCM clock net synthesis as well as VLSI clock net synthesis     

铯原子钟速度分布的计算机模型

基于已建立的小型铯原子钟计算机模型系统,研究了铯束原子速度为双峰分布和三峰分布对原子钟微波频谱的影响。分析了在此条件下的钟跃迁微波频谱的主要变化特征,并与文献报道的NBS4磁选态铯原子钟情形和北京大学的小型光抽运铯原子钟的实验结果作了比较和分析,证实束原子速度为双峰分布时微波谱所表现的特征。