H型栅结构的亚微米PDSOI MOS器件的跨导双峰效应研究

A bimodal effect of transconductance was observed in narrow channel PDSOI sub-micron H-gate PMOSFETs,which was accompanied with the degeneration of device performance.This paper presents a study of the transconductance bimodal effect based on the manufacturing process and electrical properties of those devices.It is shown that this effect is caused by a diffusion of donor impurities from the NC region of body contact to the PC poly gate at the neck of the H-gate,which would change the work function differences of the polysilicon gate and substrate.This means that the threshold voltage of the device is different in the width direction,which means that there are parasitic transistors paralleled with the main transistor at the neck of the H-gate.The subsequent devices were fabricated with layout optimization,and it is demonstrated that the bimodal transconductance can be eliminated by mask modification with NC implantation more than 0.2 m away from a poly gate.     

A universal electron mobility model of strained Si MOSFETs based on variational wave functions

A new model is proposed to describe the electron mobility enhancement in strained Si MOSFETs inversion layers using the variational wave functions in the triangular potential approximation. Phonon scattering and surface roughness scattering are included in this model and electron mobility enhancements due to the suppression of these two scatterings are accounted for, respectively. A process-dependent interface parameter is introduced to fit with various technologies. Results from the model show good agreement with experiments for different Ge mole fractions and for a wide range of vertical effective field and temperature. The model is very interesting for implementation in conventional device simulators.     

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using $hbox{N}^{+}$ poly-Si as a lower gate material and $hbox{P}^{+}$ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.      

Threshold voltage of small-geometry Si MOSFETs

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.     

大跨导n型Si/SiGe调制掺杂场效应晶体管

报道了第一支0.25μm栅长n型Si/SiGe调制掺杂场效应晶体管的制作和器件特性结果。器件用于超高真空/化学汽相淀积(UHV/CVD)制作的器件,在300K(77K)下,应变Si沟道的迁移率和电子薄层载流子的深度为1500(9500)cm~2/V·s和2.5×10~(12)(1.5×10~(10))cm~(-2)。器件电流和跨导分别为325mA/mm和600mS/mm。这些值远优于Si MESFET,它们可与所获得的GaAs/Al-GaAs调制掺杂晶体管的结果相媲美。     

Flicker noise in MOSFETs with gate-voltage-dependent mobility

Flicker noise measurements in MOSFETs at low drain bias are explained in terms of the dependence of the carrier mobility on the gate voltage of the form μ₀₀[1 + β(V_G ? V_T ? V₀)]^?1. Excellent agreement, both for the (I_d, V_g) characteristic and for the flicker noise, is obtained. The noise current spectrum is expressed in the normalized functions f(y₀, y₁) and f(y₀, y₁)/y₀ in terms of the bias parameters y₀ = β(V_g ? V_T) and y₁ = β(V_g ? V_T ? V_d).     

Hall mobility in hafnium oxide based MOSFETs: charge effects

The Hall effect is used to measure the electron mobility in HfO/sub 2/ based n-channel field effect transistors with poly-Si gates. Large deviations between measured Hall and drift mobilities are explained by the presence of high concentrations of nonfixed charge (up to 4/spl times/10/sup 12/ cm/sup -2/). Simulated mobility curves show that the observed concentrations of fixed and nonfixed charge can estimate the measured mobility significantly better than if only the fixed charge concentration is used.     

p-channel germanium MOSFETs with high channel mobility

The fabrication and performance of p-channel germanium MOSFETs having a nitrided native oxide gate insulator are reported. A self-aligned dummy-gate process suitable for circuit integration is utilized. Common-source characteristics exhibit no looping and indicate a peak room-temperature channel mobility of 770 cm²/V-s. These results provide further evidence that a high-performance germanium CMOS technology is possible     

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.     

Universality of electron mobility curves in MOSFETs: a Monte Carlostudy

The universal behavior of electron mobility when plotted versus the effective field is physically studied. Due to charged centers in the silicon bulk, the oxide, and the interface, Coulomb scattering is shown to be responsible for the deviation of mobility curves. Silicon bulk-impurities have a double effect: (a) Coulomb scattering due to the charge of these impurities themselves, and (b) reduction of screening caused by the loss of inversion charge when the depletion charge is increased. The electric-field region in which mobility curves behave universally regardless of bulk-impurity concentration, substrate bias, or interface charge has been determined for state-of-the-art MOSFETs. Finally, this study shows that electron mobility must be a function of the inversion and the depletion charges rather than a simple function of the effective field     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

Channel-carrier mobility parameters for 4H SiC MOSFETs

In this paper, mobility parameters for enhancement-mode N-channel 4H SiC MOSFETs are extracted and implemented into 2-D device simulation program and SPICE circuit simulator. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide–semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (D_it) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to a good agreement with the experimental transfer characteristic.     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

Device scaling limits of Si MOSFETs and their applicationdependencies

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Electron mobility in ULSI MOSFETs: effect of interface traps andoxide nitridation

We provide a comprehensive set of electron mobility measurements at 300 K and 77 K on standard and N₂O-nitrided MOSFETs, with channel doping in the range 3.8×10¹⁷-1.25×10¹⁸ cm^-3. In such heavily-doped devices, the Fermi level always lies very close to the conduction band edge, where interface traps reach the highest density and the shortest lifetimes. We show that these traps contribute to the gate-channel capacitance, leading to a systematic overestimate of the channel charge. This effect has the largest impact precisely in the roll-off region of the mobility curves, which has been the subject of recent theoretical investigations     

Effect of radiation-induced oxide-trapped charge on mobility inp-channel MOSFETs

It is shown that radiation-induced oxide-trapped charge contributes to an increase in mobility in p-channel MOSFETs. A new scattering mechanism involving retardation of surface-roughness scattering due to oxide-trapped charge is proposed in order to explain the observed mobility increase     

Improved split C-V method for effective mobility extraction in sub-0.1-/spl mu/m Si MOSFETs

The feasibility of split capacitance-voltage (C-V) measurements in sub-0.1 /spl mu/m Si MOSFETs is demonstrated. Based on the split C-V measurements, an improved methodology to extract accurately the effective channel length and the effective mobility is proposed. Unlike conventional I/sub d/(V/sub g/)-based extraction techniques, this new approach does not assume the invariance of the effective mobility with gate length (assumption proved to be false in this paper). This method is relevant to study transport limitations in ultimate MOSFETs as illustrated with the study of pocket implant influence on 50-nm p-MOSFETs.