具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

于混合信号片上系统的低相位噪声锁相环设计

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixed-signal SoCs with a wide range of operating frequencies. The design proposes a multi-regulator PLL architecture, in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator, reducing the parasitic noise and spur coupling between different PLL building blocks. Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-f_vco/1%-V_DD. The design is fabricated in 0.13 μ m 1.5/3.3 V CMOS technology. The in-band phase noise of –102 dBc/Hz at 1 MHz offset with a spur of less than –45 dBc is measured from 1.25 GHz carrier. The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency. The total power consumption is 19 mW, and its active area is 0.19 mm².     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

GHz band frequency hopping PLL-based frequency synthesizers

In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.     

具有工艺补偿和毛刺消除功能的快速锁定频率预置锁相环频率综合器

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.     

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4.8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0.25μm SMIC CMOS process.The oscillator consumes 6mA from 2.5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4.8GHz.Measured phase noise at 1MHz away from the carrier in this 4.8GHz VCO with symmetrical noise filter is －123.66dBc/Hz.This design is suitable for the usage in a phase-locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.     

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixedsignal SoCs with a wide range of operating frequencies.The design proposes a multi-regulator PLL architecture,in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator,reducing the parasitic noise and spur coupling between different PLL building blocks.Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-f_(vco)/1%-V_(DD).The design...     

采用PMOS底部电流源的低功耗电流自调整压控振荡器

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

A 4.2-5 GHz,low phase noise LC-VCO with constant bandwidth and small tuning gain

As the tuning frequency of an integrated LC-voltage controlled oscillator （LC-VCO） increases, it is difficult to co-design the active negative resistance core and the varactor to achieve wideband frequency range, low phase noise, constant bandwidth and small tuning gain together. The presented VCO solves the problem by designing a set of changeable varactor units. The whole VCO was implemented in a 0.18μm CMOS process. The measured result shows -120 dBc/Hz phase noise at 1 MHz offset. The measured tuning range is from 4.2 to 5 GHz and the tuning gain is 8-10 MHz/V. The VCO draws 4 mA from a 1.5 V supply voltage.     

Software Radio——Software Radio： A Review of Design Considerations and Digital Hardware Choices

This paper reviews the requirements for Software Defined Radio （SDR） systems for high-speed wireless applications and compares how well the different technology choices available- from ASICs, FPGAs to digital signal processors （DSPs） and general purpose processors （GPPs） - meet them.     

EEFA： Energy Efficiency Frame Aggregation Scheduling Algorithm for IEEE 802.11n Wireless Network

Packet size is restricted due to the error-prone wireless channel which drops the network energy utilization. Furthermore, the frequent packet retransmissions also lead to energy waste. In order to improve the energy efficiency of wireless networks and save the energy of wireless devices, EEFA （Energy Efficiency Frame Aggregation）, a frame aggregation based energy-efficient scheduling algorithm for IEEE 802.11n wireless network, is proposed. EEFA changes the size of aggregated frame dynamically according to the frame error rate, so as to ensure the data transmission and retransmissions completed during the TXOP and reduce energy consumption of channel contention. NS2 simulation results show that EEFA algorithm achieves better performance than the original frame-aggregation algorithm.     

SDN-Based Data Offioading for 5G Mobile Networks

The rapid growth of 3G/4G enabled devices such as smartphones and tablets in large numbers has created increased demand formobile data services.Wi-Fi offloading helps satisfy the requirements of data-rich applications and terminals with improved multi-media.Wi-Fi is an essential approach to alleviating mobile data traffic load on a cellular network because it provides extra capaci-ty and improves overall performance.In this paper,we propose an integrated LTE/Wi-Fi architecture with software-defined net-working(SDN)abstraction in mobile backhaul and enhanced components that facilitate the move towards next-generation 5G mo-bile networks.Our proposed architecture enables programmable offloading policies that take into account real-time network condi-tions as well as the status of devices and applications.This mechanism improves overall network performance by deriving real-time policies and steering traffic between cellular and Wi-Fi networks more efficiently.     

应力和电阻率可控的适用于高品质因子MEMS器件的原位掺硼LPCVD多晶硅薄膜

The simultaneous control of residual stress and resistivity of polysilicon thin films by adjusting the deposition parameters and annealing conditions is studied. In situ boron doped polysilicon thin films deposited at 520 ℃ by low pressure chemical vapor deposition （LPCVD） are amorphous with relatively large compressive residual stress and high resistivity. Annealing the amorphous films in a temperature range of 600-800 ℃ gives polysilicon films nearly zero-stress and relatively low resistivity. The low residual stress and low resistivity make the polysilicon films attractive for potential applications in micro-electro-mechanical-systems （MEMS） devices, especially in high resonance frequency （high-f） and high quality factor （high-Q） MEMS resonators. In addition, polysilicon thin films deposited at 570 ℃ and those without the post annealing process have low resistivities of 2-5 mΩ·cm. These reported approaches avoid the high temperature annealing process （〉 1000 ℃）, and the promising properties of these films make them suitable for high-Q and high-f MEMS devices.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

适用于双金属栅集成的TaN湿法腐蚀

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

基于非线性DAC的高速直接数字频率合成器

This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.     

掉电后SRAM防数据残留物理攻击的安全策略

This paper presents a security strategy for resisting a physical attack utilizing data remanence in powered- off static random access memory （SRAM）. Based on the mechanism of physical attack to data remanence, the strategy intends to erase data remanence in memory cells once the power supply is removed, which disturbs attackers trying to steal the right information. Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation. Implemented in 0.25μm Huahong-NEC CMOS technology, an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2 μs and data remanence is successfully eliminated. Compared with conventional SRAM, the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.     

一种应用于频率综合器的全差分电荷泵的设计与噪声分析

A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.     

Software-Defined Cellular Mobile Network Solutions

The emergency relating to software-defined networking(SDN),especially in terms of the prototype associated with OpenFlow,pro-vides new possibilities for innovating on network design.Researchers have started to extend SDN to cellular networks.Such newprogrammable architecture is beneficial to the evolution of mobile networks and allows operators to provide better services.Thetypical cellular network comprises radio access network(RAN)and core network(CN);hence,the technique roadmap diverges intwo ways.In this paper,we investigate SoftRAN,the latest SDN solution for RAN,and SoftCell and MobileFlow,the latest solu-tions for CN.We also define a series of control functions for CROWD.Unlike in the other literature,we emphasize only software-defined cellular network solutions and specifications in order to provide possible research directions.