利用Z87200实现直接序列扩频基带系统

介绍了Zilog 公司生产的Z87200直接序列扩频数字收发芯片的工作原理。该芯片是一种高智能化、可编程的扩频收发芯片。本文对该芯片部分寄存器的设置作了介绍,并针对该芯片提出了一种使用CPLD 进行时序控制的扩频系统基带部分的实现方案。     

基于数字电视基带SoC芯片的可测性设计

介绍了基于数字电视基带SoC芯片的可测性设计方案.根据系统中不同模块的特点采取有针对性的可测性设计方案,对片内存储器进行内建自测试;对组合逻辑电路、时序逻辑电路采用近全扫描的测试方案;最后采用IEEE1149.1的控制单元作为芯片可测性设计部分的控制单元,控制芯片的测试功能.经测试,该可测性设计满足设计规划的面积和功耗的要求,并且系统的测试覆盖率达到了99.26%.     

通信与网络

用于GSM/EDGE无线基站的集成中频/基带分集接收器美国模拟器件公司(ADI)近日发布了业界首款应用于GSM/EDGE无线基站的集成中频/基带分集接收器——AD6650。这种新的接收器在一块芯片内有七个单元电路,所以它只需现有解决方案50％的成本便可使基站设计师满足增强数据速率的GSM演进方案(EDGE)标准的严格要求。AD6650是凭借ADI公司的高性能数据     

一种降低基带芯片功耗的时钟策略及改进方案

为了更为有效地降低手机基带芯片中GSM通讯模块的功耗,将门控时钟策略和GSM通讯模块的特点结合起来,用硬件电路精确控制GSM通讯模块的休眠,并且对可能遇到提前唤醒的场景提出了改进方法,EDA软件仿真和FPGA验证了该方法可以达到明显的功耗优化效果.     

基于RPE-LTP算法的语音编码器的研究

基于GSM网络语音编码的RPE-LTP（规则脉冲激励-长时预测）语法，采用Verilog硬件描述语言，依托Cadence的NC-Verilog平台，完成了算法的仿真实现，并对RPE编码模块作了改进，结果可为GSM物理层基带关键技术提供支持。     

一种基于NAND FLASH基带数据模拟源的设计与实现

针对卫星数传分系统基带数据模拟源的要求,提出了基于FPGA控制的NAND FLASH解决方案,阐述了该方案的硬件和软件的设计与实现,对NAND FLASH的读、写、擦除的操作时序进行了研究。单片FLASH最高读取速率可达250 Mbps,可通过多片FLASH芯片并行读取达到更高的读取速率。试验表明,该方案实现的卫星数传分系统基带数据模拟源可以有效模拟卫星数传分系统所需的数据模拟源,满足卫星数传分系统测试的需求。     

展讯通信与CEVA达成合作伙伴关系

近日,CEVA和展讯通信联合宣称:展讯已经开始在中国市场上销售植入CEVA-TeakliteDSP核的2G/2.5GGSM/GPRS模块和基带芯片。两家公司还联合声明:他们将扩大彼此之间的合作,在实现3G的无线通信标准中,展讯将继续使用CEVA-Teak更高性能的DSP核。展讯已经开始向其客户提供SC6600型号的GSM/GPRS基带芯片,其中使用的就是CEVA-Teaklite的DSP核。SC6600是高度整合的GSM/GPRS混合信号单基带芯片,同时实现了GSM/GPRS无线通信终端所需的数字和模拟信号处理的功能。SC6600同时提供语音和数据功能,可被应用在GSM/GPRS三频手机…     

天碁科技TD-SCDMA／GSM双模终端解决方案省电率先达到商业化水平

近日,TD-SCDMA终端芯片方案提供商天碁科技宣布其TD-SCDMA/GSM双模终端解决方案已率先实现省电功能,手机演示过程通话时间达3.5个小时,待机时间超过100小时。该成果表明TD-SCDMA终端产品研发获又一重大突破,TD-SCDMA/GSM双模终端在省电性能方面已达到商业化水平。天碁科技在TD-SCDMA基带核心芯片低功耗设计和TD-SCDMA/GSM双模终端解决方案低功耗设计方面取得重大突破,使TD-SCDMA终端向商用化又迈出了坚实一步,并率先为手机生产厂家提供了成熟的低功耗TD-SCDMA手机方案。此次演示采用基于天碁科技TD-SCDMA/GSM…     

E-GOLDradio CMOS单芯片解决方案成就低成本GSM系统

E-GOLDradio是英飞凌科技公司在利用标准CMOS技术实现数字、混合信号和射频功能的一种GSM单芯片集成方案。E-GOLDradio由基带控制功能模块、四频射频收发器和GSM系统所需的混合信号构件等组成。通过减少电容器和分立式元件等外接组件．将材料成本降低了约30％。该芯片的高集成性和超小尺寸,使翻盖手机或滑盖手机的设计能实现更大的灵活性。     

双频双模导航基带芯片的静态时序分析

针对一款双频双模导航基带芯片的ASIC设计,提出一种多异步时钟域的时序约束设计方法,并通过设置虚假路径、多周期路径和修正建立保持时间违例的方法,优化了时序。最终使芯片满足系统时序要求,通过了静态时序验证,为芯片流片提供了可靠保证。     

Physical Layer Development Framework for OsmocomBB

The open source GSM protocol stack of the OsmocomBB project offers a versatile development environment regarding the data link and network layer. There is no solution available for developing physical layer baseband algorithms in combination with the data link and network layer. In this paper, a baseband development framework architecture with a suitable interface to the protocol stack of OsmocomBB is presented. With the proposed framework, a complete GSM protocol stack can be run and baseband algorithms can be evaluated in a closed system. It closes the gap between physical layer signal processing implementations in Matlab and the upper layers of the OsmocomBB GSM protocol stack. An embedded version of the system has been realized with FPGA and PowerPC to enable real-time operation. The functionality of the system has been verified with a testbed comprising an OpenBTS base-station emulator, a receiver board with RF transceiver and our developed physical layer signal processing system.     

A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer

Recent trends in the integration of entire systems on-chip have spurred the development of homodyne radios as alternatives to the more mature yet harder to integrate superheterodyne architectures. This paper presents a monolithic device that integrates all of the functions necessary to implement a multiband homodyne global system for mobile telecommunications (GSM) radio except for the power amplifier (PA) and radio frequency (RF) passives. The single BiCMOS chip includes a quad-band direct conversion receiver that down converts RF to quadrature analog baseband. The front-end circuitry is followed by a low-DC-offset, high-dynamic-range, analog I/Q baseband chain. The transmit section is comprised of a quad-band up-conversion transmit phase-locked loop (PLL) including on chip transmit voltage-controlled oscillators (VCOs). The stringent GSM receive band phase noise specifications are met without the use of surface acoustic wave filters. A single /spl Sigma//spl Delta/ fractional-N synthesizer locking a fully integrated ultrahigh frequency VCO generates the system local oscillator signal.     

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.     

基于物理层安全的最优化跨层调度方案

无线网络的调度方案要求以链路质量、传输率和时延等网络参数作为主要参考依据,控制和管理网络中节点的传输行为。现有的无线网络调度方案中都没有把网络安全纳入考虑,但是通常情况下,网络安全正是影响网络性能的重要因素。文中设计了一个新的无线网络调度方案,该方案可以在物理层实现通信的完美保密。通过把这个调度方案和IEEE802.11的Mac协议中已有的分布式协调功能(DCF)相结合,从而可以实现一个保证了物理层安全的新Mac协议——SecDCF。文中采用Matlab对该协议进行仿真,仿真结果显示在实现物理层安全的前提下,SecDCF相比传统的DCF可以显著提升性能。     

A 3 V GSM codec

Designed to satisfy the data conversion requirements of the Pan-European (GSM) cellular radio system, the chip is part of a four chip-set total GSM solution comprising the codec, the DSP, the digital ASIC, and the micro-controller. Fabricated in a 0.8 μm double-poly, double-metal CMOS process, the integrated circuit combines a voiceband codec with a baseband codec plus auxiliary converters in an 80-pin TQFP package while running off a single 3 V power supply     

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.     

MDSP-II: a 16-bit DSP with mobile communication accelerator

This paper describes a 16-bit programmable fixed-point digital signal processor, called MDSP-II, for mobile communication applications. The instruction set of MDSP-II was determined after a careful analysis of the Global System for Mobile communications (GSM) baseband functions. An application-specific hardware block called the mobile communication accelerator (MCA) was incorporated on chip to accelerate the execution of the key operations frequently appearing in Viterbi equalization. With the assistance of MCA, the GSM baseband functions, which need 53 million instructions per second (MIPS) on the general-purpose digital signal processors, can be performed only with 19 MIPS. The MDSP-II was implemented with a 0.6-μm triple-layer metal CMOS process on a 9.7×9.8 mm² silicon area and was operated up to 50 MHz clock frequency     

A software-defined communications baseband design

Software-defined radios offer a programmable and dynamically reconfigurable method of reusing hardware to implement the physical layer processing of multiple communications systems. An SDR can dynamically change protocols and update communications systems over the air as a service provider allows. In this article we discuss a baseband solution for an SDR system and describe a 2 Mb/s WCDMA design with GSM/GPRS and 802.11b capability that executes all physical layer processing completely in software. We describe the WCDMA communications protocols with a focus on latency reduction and unique implementation techniques. We also describe the underlying technology that enables software execution. Our solution is programmed in C and executed on a multithreaded processor in real time.     

A CMOS highly linear channel-select filter for 3G multistandardintegrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm² in a 0.5-μm chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA