High-temperature operation of oxide SFQ-circuit-elements

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.     

Metamorphic InP/InGaAs heterojunction bipolar transistors on GaAssubstrate: DC and microwave performances

High-performance InP/In_0.53Ga_0.47As metamorphic heterojunction bipolar transistors (MHBTs) on GaAs substrate have been fabricated using In_xGa_1-xP strain relief buffer layer grown by solid-source molecular beam epitaxy (SSMBE). The MHBTs exhibited a dc current gain over 100, a unity current gain cutoff frequency (f_T) of 48 GHz and a maximum oscillation frequency (f_MAX) of 42 GHz with low junction leakage current and high breakdown voltages. It has also been shown that the MHBTs have achieved a minimum noise figure of 2 dB at 2 GHz (devices with 5×5 μm ² emitter) and a maximum output power of 18 dBm at 2.5 GHz (devices with 5×20 μm² emitter), which are comparable to the values reported on the lattice-matched HBTs (LHBTs). The dc and microwave characteristics show the great potential of the InP/InGaAs MHBTs on GaAs substrate for high-frequency and high-speed applications     

A niobium nitride-based analog to digital converter using rapidsingle flux quantum logic operating at 9.5 K

An analog to digital converter (ADC) using the rapid single flux quantum (RSFQ) logic family implemented in niobium nitride (NbN) technology is described. The circuit was originally developed and demonstrated in niobium technology. An identical circuit was then laid out, fabricated and demonstrated in NbN technology. The chips were fabricated using an eight-layer NbN-based process with Josephson junction critical current density of 500 A/cm². In this paper, we report on the measurement results for a 6-bit flux quantizing ADC which exhibited proper operation and good DC bias margins. We also demonstrate results from an ADC chip operating up to 9.5 K     

New submicron HBT IC technology demonstrates ultra-fast, low-powerintegrated circuits

A new submicron HBT-based integrated circuit technology has been developed to fabricate transistors as small as 0.2 μm² emitter geometry. Using this novel process approach we have been able to reduce our minimum device geometry by a factor of more than ten, and reduce the metallization pitch by a factor of two compared to our baseline process. At the same time, the device RF performance improved by a factor of two. Submicron heterojunction bipolar transistors (HBT's) fabricated with this process exhibited f_T and f_max values greater than 165 and 140 GHz, respectively, and dc current gain of over 50. We have also demonstrated several circuits using submicron HBT's in this new IC technology. In particular, a latching comparator circuit which is a key building block of analog-to-digital converters, performed at 40 GHz. It exhibited three times the speed, one-third the dc power, and one-third the chip size of a similar circuit in our baseline process. A single-chip, PLL-based clock and data recovery circuit was fully functional at 4 GHz with a power supply voltage of 2.5 V. It consumed a total dc power of 50 mW, including input and output buffers     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

RSFQ 1024-bit shift register for acquisition memory

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of ±23% and ±14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO_x /Nb process with a junction critical current density of 1.0 kA/cm ²     

High-efficiency X-band GaAs IMPATT diodes

Epitaxial GaAs diodes have been fabricated giving 65¹mW CW output power at 10 GHz under room temperature operation. A dc to RF efficiency of 10.1 percent was obtained from a diode operating CW while the measured output of another diode was over 20 mW for 3 mA dc with 70-volt biasing.     

Optical input/output interface system for Josephson junctionintegrated circuits

An optical input/output interface system for a Josephson junction integrated circuit is fabricated and tested. The system consists of a superconducting optical detector, a dc powered Josephson circuit, a dc powered Josephson high voltage circuit, a liquid-He-cooled semiconductor amplifier, and a liquid-He-cooled semiconductor laser. Features of the system are use of an ultrathin NbN film for the optical detector and adoption of the dc powered Josephson circuits for logic operation circuits. Correct optical output signal is detected by a liquid-He-cooled semiconductor photodiode. The optical input/output interface has the advantage of low heat penetration and low crosstalk compared to the interface using conventional coaxial lines. Moreover, dc powered Josephson circuits have an advantage of low crosstalk from power supply lines compared to conventional Josephson circuits, which are driven by ac supply current     

Dual-Mode Terahertz Extended Interaction Oscillator Driven by a Pseudospark-Sourced Sheet Electron Beam

A terahertz dual-mode extended interaction oscillator (EIO) driven by a pseudospark-sourced sheet electron beam (SEB) was presented. The major advantages of the newly developed circuit include 1) high-density SEB interacting with the TM₁₁ and TM₃₁ modes, respectively, and 2) high output power of over 1 kW at the sub-terahertz frequency range. Two different types of 2π modes and their output characteristics were studied, and the circuit was optimized to ensure efficient outputs of two standing-wave modes. The three-dimensional (3D) particle-in-cell (PIC) simulation predicts the maximum output power of 1.3 kW with the 3-dB bandwidth of ~0.5 GHz at 303 GHz when operating at the TM₁₁ mode, and 3.18 kW with the 3-dB bandwidth of ~0.85 GHz at 364 GHz when operating at the TM₃₁ mode.     

GaInP/GaAs HBTs for high-speed integrated circuit applications

The use of GaInP/GaAs heterojunction bipolar transistors (HBTs) for integrated circuit applications is demonstrated. The discrete devices fabricated showed excellent DC characteristics with low V_ce offset voltage and very low temperature sensitivity of the current gain. For a non-self-aligned device with a 3-μm×1.4-μm emitter area, f_T was extrapolated to 45 GHz and f_max was extrapolated to 70 GHz. The measured 1/f noise level was 20 dB better than that of AlGaAs HBTs and comparable to that of low-noise silicon bipolar junction transistors, and the noise bump (Lorentzian component) was not observed. The fabricated gain block circuits showed 8.5 dB gain with a 3-dB bandwidth of 12 GHz, and static frequency dividers (divide by 4) were operable up to 8 GHz     

A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-μm technology occupies 0.09 mm²; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV_pk single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input     

InGaAs/InAlAs/InP collector-up microwave heterojunction bipolartransistors

Collector-up InGaAs/InAlAs/InP heterojunction bipolar transistors (HBTs) were successfully fabricated, and their DC and microwave characteristics measured. High collector current density operation (J_c>30 kA/cm²) and high base-emitter junction saturation current density (J₀>10^-7 A/cm²) were achieved. A cutoff frequency of f _t=24 GHz and a maximum frequency of oscillation f _max=20 GHz at a collector current density of J₀ =23 kA/cm² were achieved on a nominal 5-μm×10-μm device     

V-Band GaAs pHEMT Cross-Coupled Sub-Harmonic Oscillator

A$V$-band cross-coupled sub-harmonic injection-locked oscillator has been designed and fabricated using 0.15-$mu$m GaAs pHMET technology. Based on the known harmonic injecting circuit topology, this oscillator was designed by a differential output approach, a low-$Q$microstrip-line resonator, and a current mirror, which has a free-running oscillation frequency around 60GHz with a tuning range of 2.5GHz (from 57.8GHz to 60.3GHz). The maximum single-end output power is 3.8dBm with a dc dissipation of 225mW under a$-$3V supply voltage. Within the input matching network for second (30GHz) and fourth (15GHz) sub-harmonic signals injection, it demonstrates the maximum locking ranges close to 120MHz and 30MHz, respectively.     

Temperature-dependence investigation of a high-performance inverteddelta-doped V-shaped GaInP/InxGa1-xAs/GaAspseudomorphic high electron mobility transistor

A newly designed inverted delta-doped V-shaped GaInP/In_xGa_1-xAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) has been successfully fabricated and studied. For a 1×100 μm² device, a high gate-to-drain breakdown voltage over 30 V at 300 K is found. In addition, a maximum transconductance of 201 mS/mm with a broad operation regime for 3 V of gate bias (565 mA/mm of drain current density), a very high output drain saturation current density of 826 mA/mm, and a high DC gain ratio of 575 are obtained. Furthermore, good temperature-dependent performances at the operating temperature ranging from 300 to 450 K are found. The unity current gain cutoff frequency f_T and maximum oscillation frequency f_max up to 16 and 34 GHz are obtained, respectively. Meanwhile, the studied device shows the significantly wide and flat gate bias operation regime (3 V) for microwave performances     

Noise performance at cryogenic temperatures at AlGaAs/InGaAs HEMT'swith 0.15-μm T-shaped WSix gates

T-shaped 0.15-μm WSi_x gate HEMTs have been fabricated on AlGaAs/InGaAs MBE wafers. Their S-parameters, output noise spectral density P_no, and noise temperatures T _e at cryogenic temperatures, were measured. The current gain cutoff frequency f_T increases from 61 GHz at 295 K to 87 GHz at 90 K. P_no and T_e measurements indicate that the hot-electron effect is noticeable at low temperatures at high drain current. At 30 GHz, the noise temperature is 19±3 K with an associated gain of 10.4 dB at the physical temperature of 20 K. The results demonstrate the great potential of AlGaAs/InGaAs HEMTs for low-temperature applications     

A 850-GHz waveguide receiver employing a niobium SIS junctionfabricated on a 1-μm Si3N4 membrane

We report on a 850-GHz superconducting-insulator-superconducting (SIS) heterodyne receiver employing an RF-tuned niobium tunnel junction with a current density of 14 kA/cm², fabricated on a 1-μm Si₃N₄ supporting membrane. Since the mixer is designed to be operated well above the superconducting gap frequency of niobium (2Δ/h≈690 GHz), special care has been taken to minimize niobium transmission-line losses. Both Fourier transform spectrometer (FTS) measurements of the direct detection performance and calculations of the IF output noise with the mixer operating in heterodyne mode, indicate an absorption loss in the niobium film of about 6.8 dB at 822 GHz. These results are in reasonably good agreement with the loss predicted by the Mattis-Bardeen theory in the extreme anomalous limit. From 800 to 830 GHz, we report uncorrected receiver noise temperatures of 518 or 514 K when we use Callen and Welton's law to calculate the input load temperatures. Over the same frequency range, the mixer has a 4-dB conversion loss and 265 K±10 K noise temperature. At 890 GHz, the sensitivity of the receiver has degraded to 900 K, which is primarily the result of increased niobium film loss in the RF matching network. When the mixer was cooled from 4.2 to 1.9 K, the receiver noise temperature improved about 20% 409-K double sideband (DSB). Approximately half of the receiver noise temperature improvement can be attributed to a lower mixer conversion loss, while the remainder is due to a reduction in the niobium film absorption loss. At 982 GHz, we measured a receiver noise temperature of 1916 K     

A temperature-dependent nonlinear analysis of GaN/AlGaN HEMTs usingVolterra series

Gain and intermodulation distortion of an AlGaN/GaN device operating at RF have been analyzed using a general Volterra series representation. The circuit model to represent the GaN FET is obtained from a physics-based analysis. Theoretical current-voltage characteristics are in excellent agreement with the experimental data. For a 1 μm×500 μm Al_0.15Ga_0.85N/GaN FET, the calculated output power, power-added efficiency, and gain are 25 dBm, 13%, and 10.1 dB, respectively, at 15-dBm input power, and are in excellent agreement with experimental data. The output referred third-order intercept point (OIP₃) is 39.9 dBm at 350 K and 33 dBm at 650 K. These are in agreement with the simulated results from Cadence, which are 39.34 and 35.7 dBm, respectively. At 3 GHz, third-order intermodulation distortion IM₃ for 10-dBm output power is -72 dB at 300 K and -56 dB at 600 K. At 300 K, IM₃ is -66 dB at 5 GHz and -51 dB at 10 GHz. For the same frequencies, IM ₃ increases to -49.3 and -40 dB, respectively, at 600 K     

High temperature performance of NMOS integrated inverters and ringoscillators in 6H-SiC

Electrical characterization up to 573 K is performed on integrated inverters with different beta ratios and 17-stage ring oscillators based on SiC NMOS technology. These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration of N_A=1·10 ¹⁶ cm^-3. The n⁺ source/drain regions and buried channels for depletion-mode load transistors are achieved by ion implantation of nitrogen. Direct current measurements of the inverters with a 5 V power supply yield proper output levels and acceptable noise margins both at 303 and 573 K. Dynamic measurements with square waves show the full voltage swing up to 5 kHz in this temperature range. The 17-stage ring oscillators, driven by a 5.5 V power supply, show an oscillator frequency of 625 kHz at 303 K, which corresponds to a 47 ns delay per inverter stage. This time constant increases only to 59 ns at 573 K. The temperature drift of the measured output signal is well below 30% up to this elevated temperatures. During 20 heat cycles up to 573 K in air, no measurable drift in circuit parameters occurred. In addition, only a slight dependence of the oscillator frequency on supply voltage is observed     

Ferroelectric neuron integrated circuits using SrBi2Ta2O9-gate FET's and CMOS Schmitt-triggeroscillators

A pulse frequency modulation (PFM) type ferroelectric neuron circuit composed of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) and a CMOS Schmitt-trigger oscillator was fabricated on an SOI structure, in which SrBi₂Ta₂O₉ (SBT) was used as a ferroelectric gate material of the FET. It was found that the fabricated MFSFET showed a relatively good I_D-V_G (drain current versus gate voltage) characteristic with a hysteresis loop due to the ferroelectricity of the SBT film and that it acted as a synapse device with adaptive-learning function. It was also found that the output pulse height of the circuit was as high as the power supply voltage and that output pulse frequency was changed as the number of applied input pulses increased     

Novel fabrication of C-doped base InGaAs/InP DHBT structures for high speed circuit applications

We have fabricated InGaAs/InP based DHBTs for high speed circuit applications. A process involving both wet chemical and ECR plasma etching was developed. Carbon was employed as the p-type dopant of the base layer for excellent device stability. Both the emitter–base and base–collector regions were graded using quaternary InGaAsP alloys. The extrinsic emitter–base junction is buried for junction passivation to improve device reliability. The use of an InP collector structure with the graded region results in high breakdown voltages of 8-10 V, with no current blocking. The entire structure is encapsulated with spin-on-glass. These devices show no degradation in d.c. characteristics after operation at an emitter current density of 90 kA cm⁻² and a collector bias, V_CE, of 2 V at room temperature for over 500 h. Typical common emitter current gain was 50. An f_t of 80 and f_max of 155 GHz were achieved for 2×4 μm² emitter size devices.