The design, fabrication, and characterization of a novel electrode structure self-aligned HBT with a cutoff frequency of 45 GHz

This paper establishes a systematic approach for the design, fabrication, and modeling of a newly proposed self, aligned Al-GaAs/GaAs heterojunction bipolar transistor (HBT) employing a two-dimensional heterostructure device simulator and a heterojunction bi-polar transistor circuit simulator. The developed HBT has an abrupt emitter-base heterojunction, and applies a novel structure in which a single base electrode is placed between two emitter electrodes. A fabricated 3 × 8 µm²two-emitter HBT exhibits a measured current gain cutoff frequency fT= 45 GHz and a maximum oscillation frequency fmax= 18.5 GHz. Results of frequency divider circuit Simulation indicate that the developed HBT would be 1.4 times faster than a conventional HBT in which one emitter electrode is located between two base electrodes.     

Fabrication and characterization of AlGaAs/GaAs heterojunction bipolar transistors

The fabrication and characterization of MBE-grown AlGaAs/GaAs heterojunction bipolar transistors (HBT's) are described, A Be redistribution profile in the HBT epi-layer at the emitter-base heterojunction interface is investigated using secondary ion mass spectrometry, A relatively high substrate temperature of 650°C during growth can be employed by introducing a 100-Å undoped spacer layer between the emitter and base layer. A simple wafer characterization method using phototransistors is demonstrated for accurately predicting current gain in a three-terminal device. A dc current gain of up to 230 is obtained for the fabricated HBT with a heavy base doping of 1 × 10¹⁹/cm³. A gain-bandwidth product fTof 25 GHz is achieved with a 4.5-µm-width emitter HBT.     

High-performance p-n-p AlGaAs/GaAs heterojunction bipolar transistors: A theoretical analysis

The AlGaAs/GaAs P-n-p heterojunction bipolar transistor (HBT) is shown by a simple analysis to exhibit millimeter wave and digital switching performance comparable to similar N-p-n structures. For example, a P-n-p HBT with a 1-µm emitter stripe and 34-µm²total area yieldsf_{tau} = 31GHz,f_{max} = 94GHz, and an intrinsic switching speedtau_{s} = 8ps. A similar N-p-n structure exhibitsf_{tau} = 56GHz,f_{max} = 102GHz, andtau_{s} = 8ps.     

A high luminance high-resolution cathode-ray tube for special purposes

For those applications where light sources of high radiance or displays of high resolution are necessary, miniature cathode-ray tubes have been developed with monocrystalline luminescent screens. These newly developed screens consist of cerium-doped yttrium-aluminum garnet (YAG), epitaxially grown on commercially available YAG substrates; they have an excellent heat conductivity and are optically clear. The construction of the tube and its performance in two modes of operation are described. When the tube is operated with a continuous undeflected beam, the luminance of the spot is limited by thermal quenching of the phosphor material. Under these circumstances, the maximum luminance of 1.9 × 10⁸cd/m²(0.55 × 10⁸FTL or 4 × 10⁵W/m²sr) is reached at a power of 70 mW in a 3.5-µA 20-kV beam, focussed to a spot of 9 µm diameter. Equipped with appropriate deflection coils and scanned with an interlaced field of 575 active lines and 25-Hz repetition frequency, the tube can handle up to 20 W of beam power in a 12 × 16 mm²image area. In this mode, the luminance is limited by the design of the electron gun and the desired resolution. At 20 kV and 100 µA (i.e., at 7500 cd/m²) the tube has a half-intensity linewidth of 60 µm, which is equivalent to 500-TV limiting response lines in the same 12 × 16 mm²area.     

Utilization of NiSi2as an interconnect material for VLSI

The applicability of NiSi2as an interconnect material was investigated using narrow (5 µm- × 2600-µm) lines. 2500-Å-thick silicide lines were thermally oxidized to form a passivation layer of SiO2for the next metallization level. Isolation of more than 50 V for 2200-Å SiO2is achieved. The interconnect resistivity following the oxidation is 1.2-1.4 Ω. The maximum current capability of the lines was found to be > 5 × 10⁶A/cm²and their stability under prolonged high current densities was demonstrated. We propose a scheme to increase the local metallization-level density using NiSi2as an interconnect.     

Reduction of extrinsic base resistance in GaAs/AlGaAs heterojunction bipolar transistors and correlation with high-frequency performance

Improved high-frequency performance in GaAs/AlGaAs heterojunction bipolar transistors (HBT's) by reduction of extrinsic base resistance is demonstrated. A new self-aligned process which is very simple, yet capable of producing 0.25-µm emitter-to-base contact gaps, is described. By the use of AuBe, we have also been able to produce contact resistances to p-type GaAs (p = 5 × 10¹⁸) as low as 1.2 × 10^-7Ω.cm². This is the lowest value reported to p-type GaAs considering the relatively low doping levels used. By employing these techniques, we have produced HBT's with 2.5-µm-wide emitters having current gain cutoff frequencies fTthat appear to be greater than 35 GHz and maximum oscillation frequenciesf_{max}of 22 GHz.     

Small-scaled InGaP/GaAs HBTs with WSi/Ti base electrode and buriedSiO2

This paper describes the fabrication and characteristics of small-scaled InGaP/GaAs HBTs with high-speed as well as low-current operation. To reduce both the emitter size S_E and the base-collector capacitance C_BC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO₂ in the extrinsic base-collector region under the base electrode. WSi/Ti simplifies and facilitates processing to fabricate a small base electrode, and makes it possible to reduce the width of the base contact to less than 0.4 μm without the large increase in the base resistance. The DC current gain of 20 is obtained for an HBT with S _E of 0.3×1.6 μm² due to the suppression of emitter size effect by using InGaP as the emitter material. An HBT with SE of 0.6×4.6 μm² exhibited f_T of 138 GHz and f_max of 275 GHz at I_C of 4 mA; and an HBT with SE of 0.3×1.6 μm² exhibited f_T of 96 GHz and f_max of 197 GHz at I_C of 1 mA. These results indicate the great potential of these HBTs for high-speed and low-power circuit applications     

AlGaAs/GaAs heterojunction bipolar transistors with small size fabricated by a multiple self-alignment process using one mask

A multiple self-alignment process for HBT's using one mask is developed to form emitters, emitter contacts, emitter contact leads, buried small collectors, base contacts, and base contact leads. This process makes it possible to produce HBT's of very small size and to reduce parasitic elements. An AlGaAs/GaAs HBT fabricated by the process, with an emitter 1 × 20/µm²in size and a buried collector by O⁺implantation gives a good performance of ft= 54 GHz and fmax= 42 GHz. The performance may be explained by the reduction of parasitic elements, base transit time, and collector depletion layer transit time.     

Direct measurement of stray magnetic field distributions from a magnetic bubble domain in yttrium orthoferrite with a micro Hall element

The stray magnetic field distributions from an isolated magnetic bubble domain of about 150-µm diameter in YFeO3are measured by a micro Hall element made of a single crystal InSb with active dimensions of 5 × 5 × 2.6 µm³. Experimental results for an isolated bubble domain show fair agreement with the theoretical ones for a cylindrical bubble domain.     

Smallest p-n-p-n memory cell

Although the p-n-p-n device is suitable for a 1-bit/cell static mamory, it has not yet been put to practical use because of its large cell size. By employing a sophisticated process involving single-crystal/poly-Si simultaneous growth on the same substrate, the smallest-sized vertical p-n-p-n device has been developed. Using this cell structure, a 12-bit scanner with 21.2-MHz transfer frequency, 16-µm pitch and 10-µmW/bit power dissipation has been fabricated. This cell structure is also applied to a static RAM with 22 × 27 = 594 µm²cell size. A high switching speed as well as a high packing density is predicted by this configuration.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FET's. Estimated average electron velocity is rather high, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at room temperature (77 K). In addition,f_{max}is as high as 41 GHz. fTis 45 GHz, which is the best data ever reported in 0.5-µm gate FET's.     

Junction-current-confinement planar light-emitting diodes and optical coupling into large-core diameter fibers using lenses

High-radiance AlGaAs-GaAs double-heterostructure light-emitting diodes utilizing junction current confinement are described. Diode resistance and junction ideality factor are investigated as a function of emission diameters from 10 to 75 µm. Near-field intensity profiles indicate tight current confinement over the full range of emission diameters. Rise-time measurements are consistent with a simple carrier lifetime model for >25-µm emission diameters. An effective radiative-recombination constant, B = 1.5(±0.5) × 10-¹⁰cm³/s is deduced from the rise-time data and model. Peak wavelength and spectral width data are discussed in terms of junction current density and temperature. With decreasing emission diameter, the optical coupling efficiencies into 100- and 200-µm core diam high-numerical-aperture fibers increased from 10 to 25 percent and 25 to 50 percent, respectivley, using spherical glass lenses.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

Normally-off InGaAs junction field-effect transistor with InGaAs buffer layer

InGaAs junction field-effect transistors (JFET's) with 1-µm gate length were successfully fabricated with an n⁺-InGaAs active layer (8 × 10¹⁶cm^-3) and an undoped InGaAs buffer layer grown on semi-insulating InP:Fe substrate by liquid-phase epitaxy. The device showed good pinch-off behavior with a threshold voltage of 0.25 V, a low drain current of 1 µA at zero gate-source voltage, and a very high transconductance of 553 mS/mm at room temperature. This is one of the highest transconductance values ever reported for a 1-µm gate-length FET.     

Design and performance of very high-speed In0.53Ga0.47As/In0.52Al0.48As p-i-n photodiodes grown by molecular beam epitaxy

High-speed In0.53Ga0.47As/In0.52Al0.48As photodiodes have been grown by molecular beam epitaxy (MBE) on semi-insulating InP substrates and fabricated. The measured impulse response characteristics are very close to the analytically calculated ones. The temporal response to pulsed optical excitation is characterized by a rise time of 21 ps and a width (FWHM) of 27 ps. The 25 × 20-µm²diodes have a junction capacitance <0.1 pF, a dark current ∼1 nA, and a peak responsivity of 0.35 A/W. These characteristics are comparable or better than most epitaxial InGaAs photodiodes reported to date and make the devices suitable for a host of high-speed applications and monolithic integration.     

A 2.5-kV static induction thyristor having new gate and shorted p-emitter structures

An SI thyristor with new gate and shorted p-emitter structures (DTT-SI thyristor) is proposed to realize a high-voltage high current high-speed device having a low forward voltage drop. Investigations using fabricated 2.5-kV 100-A DTT-SI thyristors and numerical analyses show that the DTT-SI thyristor has a good trade-off between the forward voltage drop and switching characteristics when the channel width is 8-10 µm and the maximum impurity concentration is about 1 × 10¹⁷to 4 × 10¹⁷cm^-3. The typical fabricated DTT-SI thyristor has a 2.5-kV forward blocking voltage with a 58-V reverse gate bias voltage, a 1.4-V forward voltage drop with a 100-A anode current, a 2- µs turn-on time, adi/dtcapability higher than 4000 A/µs, and can interrupt a 900-A anode current with a 3.5-µs turn-off time and a 5.6 gate turn-off gain on application of a 100-V reverse gate bias voltage.     

A vertically isolated self-aligned transistor—VIST

A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10^-8A. The ftvalue of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm²transistor cell. The power and delay product is 0.12 pJ.     

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 10²⁰/cm³have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.     

Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memory

A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta2O5capacitor stacked on it. By this cell, the ultimate cell area3F times 2Fcan be realized with sufficient operating margin. Here,Fis the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta2O5film was small enough for the storage capacitor dielectric. Using a3F times 4Fcell and a4Fpitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm², and a chip size of 9.2 × 9.5 mm²were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.