超高清实时H.264/AVC编码系统设计

基于多核处理器的并行计算能力,设计并实现实时超高清分辨率(3 840×2 160)的H.264/AVC视频编码系统。该系统在原始像素输入端实现高效的内存管理,超高清编码器采用帧级、条带级、指令级的并行方案,码流输出端则采用FIFO缓冲器对RTP包的传输速度进行控制。实验结果表明,编码系统能实时对超高清视频源进行并行编码,通过RTP封装格式传输至IP网络,用户可使用视频播放器接收并回放。     

一种基于DSP的H.264到H.263实时转码器

设计了一种基于DSP的H.264到H.263实时转码器,充分利用视频编解码过程的冗余信息,对传统结构的转码器进行改进,降低了转码运算复杂度.结合TMS320DM642的特点在DSP平台上完成了这两种转码器的优化实现.最终实验数据表明,传统结构转码器优化后转码速度能达到20f/s(帧/秒),而所设计的转码器则能实现CIF格式25f/s从H.264到H.263的实时转码,并且没有显著的视频质量损失.     

基于流体系结构的帧内预测算法优化设计

为高效实现H.264多模式帧内预测,解决其计算复杂度高造成的计算压力,本文根据H.264帧内预测算法的计算密集与数据并行的特征,基于流处理执行模型提出适用于Imagine流体系结构的分组帧内预测流算法,并采用长流分段技术进行优化设计.实验结果表明,H.264帧内编码器流实现对1280×720高清视频编码帧率达45.9fps,满足实时性需求.     

基于TILEPRO64的H.264/AVC多粒度并行编码研究

H.264/AVC视频编码标准与过去的视频编码标准相比,在编码效率上有了很大的提高。然而,较高的计算量使H.264/AVC视频编码很难在嵌入式平台上完成高清视频的实时编码,因此提出基于多核的H.264/AVC并行编码器成为必然。文章主要研究的是基于TILEPR O64多核处理器的slice级与宏块级多粒度并行编码。结果表明,在TILEPR O64多核处理器上,H.264/AVC多粒度并行编码可以取得更好的加速效果,且编码后的视频质量变化不明显。     

一种基于参数替换的H.264标准水印嵌入算法研究

随着高清数字影像的发展,H.264视频编码方法逐渐成为下一代的视频标准。H.264由于使用了帧内预测编码、运动精度为1/4像素的估计算法使它可获得MPEG-2的2倍以上的压缩比和视频质量,而获得广泛应用。但是在H.264视频中嵌入水印用传统视频水印的方法无法有效地完成,在对视频编码的帧内预测模型研究的基础上,设计了一种快速的水印嵌入算法,基本实现了在H.264编码过程中水印提取的盲检测,其低算法复杂度可以满足视频实时处理的需要。     

一种新的MPEG-2到H.264的转码算法

研究了MPEG-2到H.264的转码技术,在MPEG-2和H.264压缩算法基础上提出了一种基于MV重用和H.264多参考帧特性的转码算法.实验表明,本算法与反向查找表算法相比在转码效率和转码视频质量两方面都有所提高.     

基于众核处理器的AVS并行解码器的设计与实现

众核处理器的并行计算为AVS并行解码器的实现提供了基础,提出了一种功能并行和数据并行混合的并行设计方案,该方案采用了帧间和宏块行的两级并行。使用Tilera推出的Tile-Gx36众核处理器,同时利用该处理器提供的SIMD指令集进行了反量化、反变换、插值等模块的优化。实验结果表明该设计具有良好的并行加速比,可以在6个核的条件下完成1路AVS高清实时解码。     

基于Tilera众核处理器的AVS并行解码器的设计与实现

众核处理器的并行计算为AVS并行解码器的实现提供了基础,本文提出了一种功能并行和数据并行混合的并行设计方案,该方案采用了帧间和宏块行的两级并行。本文使用的是Tilera推出的Tile-Gx36众核处理器,同时利用该处理器提供的SIMD指令集进行了反量化、反变换、插值等模块的优化。实验结果表明该设计具有良好的并行加速比,可以在6个核的条件下完成1路AVS高清实时解码。     

AVS编码器中帧内预测模块的硬件设计

根据AVS标准中帧内预测算法的特点,提出了一种应用于AVS高清实时编码器的帧内预测硬件设计方案.该设计中将亮度和色度预测共用一个预测单元,采用6路数据并行流水处理的结构,提高了处理速度.同时在分析AVS帧内预测各模式算法的基础上,结合移位寄存器操作实现各模式运算单元的进一步资源共享,简化了参考数据选择机制,减少资源消耗.实验结果表明,该设计完全能够满足高清视频图像(1 920×1 080,30 f/s(帧/秒))实时编码要求.     

基于Tilera平台的AVS视频编码器的研究与实现

Tile处理器是Tilera公司研发的一种新型的多核处理器，文章在介绍Tilera平台的多核处理器的基础上，根据该处理器的架构特点，在该平台上实现了AVS和H.264的标清/高清实时视频编码器。     

Data-parallel intra decoding for block-based image and video coding on massively parallel architectures

With the increasing number of processor cores available in modern computing architectures, task or data parallelism is required to maximally exploit the available hardware and achieve optimal processing speed. Current state-of-the-art data-parallel processing methods for decoding image and video bitstreams are limited in parallelism by dependencies introduced by the coding tools and the number of synchronization points introduced by these dependencies, only allowing task or coarse-grain data parallelism. In particular, entropy decoding and data prediction are bottleneck coding tools for parallel image and video decoding. We propose a new data-parallel processing scheme for block-based intra sample and coefficient prediction that allows fine-grain parallelism and is suitable for integration in current and future state-of-the-art image and video codecs. Our prediction scheme enables maximum concurrency, independent of slice or tile configuration, while minimizing synchronization points. This paper describes our data-parallel processing scheme for one- and two-dimensional prediction and investigates its application to block-based image and video codecs using JPEG XR and H.264/AVC Intra as a starting point. We show how our scheme enables faster decoding than the state-of-the-art wavefront method with speedup factors of up to 21.5 and 7.9 for JPEG XR and H.264/AVC Intra coding tools respectively. Using the H.264/AVC Intra coding tool, we discuss the requirements of the algorithm and the impact on decoded image quality when these requirements are not met. Finally, we discuss the impact on coding rate in order to allow for optimal parallel intra decoding.     

An architecture of entropy decoder,inverse quantiser and predictor for multi-standard video decoding

A VLSI architecture for entropy decoder, inverse quantiser and predictor is proposed in this article. This architecture is used for decoding video streams of three standards on a single chip, i.e. H.264/AVC, AVS (China National Audio Video coding Standard) and MPEG2. The proposed scheme is called MPMP (Macro-block-Parallel based Multilevel Pipeline), which is intended to improve the decoding performance to satisfy the real-time requirements while maintaining a reasonable area and power consumption. Several techniques, such as slice level pipeline, MB (Macro-Block) level pipeline, MB level parallel, etc., are adopted. Input and output buffers for the inverse quantiser and predictor are shared by the decoding engines for H.264, AVS and MPEG2, therefore effectively reducing the implementation overhead. Simulation shows that decoding process consumes 512, 435 and 438 clock cycles per MB in H.264, AVS and MPEG2, respectively. Owing to the proposed techniques, the video decoder can support H.264 HP (High Profile) 1920 × 1088@30fps (frame per second) streams, AVS JP (Jizhun Profile) 1920 × 1088@41fps streams and MPEG2 MP (Main Profile) 1920 × 1088@39fps streams when exploiting a 200 MHz working frequency.     

Adaptive slice-level parallelism for H.264/AVC encoding using pre macroblock mode selection

In order to achieve high computational performance and low power consumption, many modern microprocessors are equipped with special multimedia instructions and multi-core processing capabilities. The number of cores on a single chip increases double every three years. Therefore, besides complexity reduction by smart algorithms such as fast macroblock mode selection, an effective algorithm for parallelizing H.264/AVC is also very crucial in implementing a real-time encoder on a multi-core system. This algorithm serves to uniformly distribute workloads for H.264/AVC encoding over several slower and simpler processor cores on a single chip. In this paper, we propose a new adaptive slice-size selection technique for efficient slice-level parallelism of H.264/AVC encoding on a multi-core processor using fast macroblock mode selection as a pre-processing step. For this we propose an estimation method for the computational complexity of each macroblock using pre macroblock mode selection. Simulation results, with a number of test video sequences, show that, without any noticeable degradation, the proposed fast macroblock mode selection reduces the total encoding time by about 57.30%. The proposed adaptive slice-level parallelism has good parallel performance compared to conventional fixed slice-size parallelism. The proposed method can be applied to many multi-core systems for real-time H.264 video encoding.     

H.264并行编码算法的研究

以X264编码器作为研究对象,在指令集并行的基础上对其进行线程级并行优化,在Intel双核处理器平台上.针对非实时编码应用得到近2倍的加速比,针对实时编码应用得到1.5倍的加速比.     

The H.264/MPEG4 advanced video coding standard and its applications

H.264/MPEG4-AVC is the latest video coding standard of the ITU-T video coding experts group (VCEG) and the ISO/IEC moving picture experts group (MPEG). H.264/MPEG4-AVC has recently become the most widely accepted video coding standard since the deployment of MPEG2 at the dawn of digital television, and it may soon overtake MPEG2 in common use. It covers all common video applications ranging from mobile services and videoconferencing to IPTV, HDTV, and HD video storage. This article discusses the technology behind the new H.264/MPEG4-AVC standard, focusing on the main distinct features of its core coding technology and its first set of extensions, known as the fidelity range extensions (FRExt). In addition, this article also discusses the current status of adoption and deployment of the new standard in various application areas.     

Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor

An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction‐level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.     

视频压缩编码国际标准综述

国际标准化组织和国际电信联盟制定了一系列视频压缩编码国际标准,有H.261,MPEG1,MPEG2, H.263, MPEG4和H.264等.该文分别对这些标准的技术特征和性能进行分析,并详细描述H.264中采用的视频编码新技术.     

一种新的基于VLIW的IDCT和运动补偿算法

本文使用矩阵形式在超长指令字(VLIW)的观点下将几种经典算法与已有的适合于VLIW的算法进行了比较.然后利用VLIW结构的特性,提出了一种快速IDCT算法.与现有算法相比,新算法进一步减少了所需的指令周期.并利用VLIW结构的寄存器特性,将视频编解码过程中的运动补偿(预测)和IDCT(DCT)组合,使运动补偿所需时间降低为原来的约50%,这种思想能应用于MPEG1/2/4,H.263和H.264.     

基于TMS320DM642的MPEG-4编码器设计和优化

给出在TMS320DM642 DSP平台上实现MPEG-4视频编码器所用到的优化方法.这些方法包括算法的改进及存储器的合理分配,以提高程序代码的并行性,减少计算量,重点是运动估计模块及其相关问题的设计优化.该编码器可以在CIF大小图像格式下以25f/s左右的速度进行编码,满足实时视频编码的要求.     

一种H.264运动估计器的VLSI设计

MPEG4AVC／ITU—T H．264视频编码标准中所采用的多模式运动估计算法与传统的MPEG4、H．263 高级预测模式相比较而言，编码效率和性能都大大提高。但其诸如模式决策等问题却给运动估计器，特别是硬件运动估计器带来非常大的运算复杂度。本文提出一种H．264运动估计器硬件结构，它采用了新的模式决策算法和快速运动估计算法。仿真结果证明，这两种算法不但能使运动估计器降低其硬件实现成本，而且能减少模式决策和运动估计的时间。