Submicrometer CMOS devices in zone-melting-recrystallized SOI films

CMOS devices with effective channel lengths ranging from 0.7 to 4.0 µm have been fabricated in zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) films prepared by the graphite-strip-heater technique. Low-temperature processing was utilized to minimize dopant diffusion along subboundaries in the films. Both n- and p-channel devices have low leakage current (<0.1-pA/µm channel width) and good subthreshold characteristics. For ring oscillators with a transistor channel length of 0.8 µm, the propagation delay is 95 ps at a supply voltage of 5 V.     

An advanced Ge preamorphization salicide technology forultra-thin-film SOI CMOS devices

In this letter, we propose a new approach to implement salicide on thin-film silicon-on-insulator (SOI) through the amorphization of the source/drain (S/D) regions by a germanium implantation. The amorphous film greatly reduces the silicide formation energy and effectively controls the silicide depth. This results in a much lower thermal cycle and increased flexibility in the choice of metal thickness. SOI NMOS devices fabricated using this novel salicide technology have shown substantially reduced S/D resistance as well as good device performance. This technology is applicable to PMOS SOI MOSFETs as well     

A new self-aligned well-isolation technique for CMOS devices

This paper presents the development of a new well-isolation technique for advanced CMOS LSI's. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

Submicrometer self-aligned dual-gate GaAs FET

Experimental results show that it is possible to fabricate dual-gate GaAs FET's, with Lg1= 0.6 µm and Lg2= 1.3 µm, using conventional photoprocessing equipment, masks, and alignment tolerances. The initial source mesa establishes both the source and drain edges during the ohmic contact metal deposition. These two edges establish the lengths and positions of the two gates in the channel, during the two subsequent evaporations. Initial experimental devices gave reasonably good small-signal microwave performance: 8-dB packaged net gain with less than 6-dB simultaneous noise figure, at 6 GHz.     

A new cobalt salicide technology for 0.15-μm CMOS devices

A new cobalt (Co) salicide technology for sub-quarter micron CMOS transistors has been developed using high-temperature sputtering and in situ vacuum annealing. Sheet resistance of 11 Ω/□ for both gate electrode and diffusion layer was obtained with 5-nm-thick Co film. No line width dependence of sheet resistance was observed down to 0.15-μm-wide gate electrode and 0.33-μm-wide diffusion layer. The high temperature sputtering process led to the growth of epitaxial CoSi ₂ layers with high thermal stability. By using this technology 0.15 μm CMOS devices which have shallow junctions were successfully fabricated     

Submicrometer fully self-aligned AlGaAs/GaAs Heterojunction bipolar transistor

A novel submicrometer fully self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) for reducing parasitic capacitances and resistances is proposed. The fabrication process utilizes SiO2sidewalls for defining base electrode width and separating this electrode from both emitter and collector electrodes. Measured common-emitter current gain β for a fabricated HBT with 0.6 × 10-µm²emitter dimension and 0.7 × 10-µm²× 2 base dimension is 26 at 9 × 10⁴-A/cm²collector current density.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

Submicrometer self-aligned AlGaAs/GaAs heterojunction bipolartransistor process suitable for digital applications

A self-aligned process is developed to obtain submicrometer high-performance AlGaAs/GaAs heterojunction bipolar transistors (HBTs) which can maintain a high current gain for emitter sizes on the order of 1 μm². The major features of the process are incorporation of an AlGaAs surface passivation structure around the entire emitter-base junction periphery to reduce surface recombination and reliable removal of base metal (Ti/W) deposits from the sidewall by electron cyclotron resonance (ECR) plasma deposition of oxide and ECR plasma etching by NF₃. A DC current gain of more than 30 can be obtained for HBTs with an emitter-base junction area of 0.5×2 μm² at submilliampere collector currents. The maximum f_T and f_max obtained from a 0.5×2 μm² emitter HBT are 46 and 42 GHz, respectively at I_C=1.5 and more than 20 GHz even at I_C=0.1 mA     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.     

Submicrometer self-aligned recessed gate InGaAs MISFET exhibiting very high transconductance

A new submicrometer InGaAs depletion-mode MISFET with a self-aligned recessed gate structure is presented. The techniques used to implement this FET structure are angle evaporation for submicrometer pattern definition and sputter etching/wet chemical etching for channel recess. Highest transconductance observed was in excess of 250 mS/mm, with 200 mS/mm as a more typical value. The very high transconductance is attributed partly to the low source series resistance achieved in this structure, typically 0.5 Ω.mm or less. From the IV characteristics of these FET's, a saturation velocity equal to 2.4 × 10⁷cm/s at the drain end was deduced.     

An advanced 0.5-μm CMOS disposable TiN LDD/salicide spacerprocess

An advanced 0.5-μm CMOS technology which features disposable TiN spacers to define both lightly doped drain (LDD) implantation and self-aligned silicided source, drain, and gate regions is discussed. Since the LDD implantation sequences are reversed using the disposable TiN spacers, this process results in CMOS devices with low salicided junction leakage, reduced source/drain lateral diffusion, and shallow phosphorus N^- and boron P^- regions for improved short-channel behavior     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Submicrometer GaAs MESFET with shallow channel and very high transconductance

A 0.5-µm GaAs MESFET with a 25-nm thin channel, 400- mS/mm maximum transconductance, and 580-mS/V.mm K value is presented. This extremely high K value was obtained using an electron-beam fabricated recessed-gate MESFET structure on a highly doped (9.10¹⁷cm^-3) MBE-grown channel layer with 2600-cm²/V.s mobility. The use of thin channels and a buried p-layer also reduced the output conductance and other short-channel effects dramatically. As a result, these scaled MESFET's are very promising for high-speed digital logic circuits.     

A high-performance BICMOS Technology with double-polysilicon self-aligned bipolar devices

A high-performance BICMOS technology is described which incorporates 12-GHz double-polysilicon self-aligned bipolar, fully salicided CMOS devices and 1-µm features. This process is applied to a new BICMOS gate design, called transistor feedback logic (TFL), to fabricate a divide-by-16 frequency divider with a maximum operating frequency of 364 MHz. Availability of uncompromised MOS and bipolar transistors allows a free mix of pure CMOS, pure bipolar, or BICMOS gates on the same chip.     

Fabrication of fully self-aligned joint-gate CMOS structures

A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and PMOS transistors have been characterized and together are functional in joint-gate CMOS inverters.     

Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi2and n⁺-p⁺source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10^-7and 1 × 10^-6Ω . cm²can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10²⁰/cm³. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n⁺and TiSi2-P⁺interfaces.     

Submicrometer CMOS device fabrication using an X-ray stepper

CMOS devices with submicrometer minimum features have been fabricated using X-ray/photo hybrid lithography. The device fabrication process utilized thirteen lithography steps, including four X-ray lithography levels, such as local oxidation of silicon (LOCOS) [1], gate, contact, and wiring, that required the most critical dimension control and alignment accuracy. A step and repeat exposure system and a SiNxmembrane mask were used for the X-ray lithography process. The SiNxmembrane mask was improved in its flatness and effective contrast by employing a stress compensating structure and a secondary electron trapping film. As a result, CMOS devices with 0.4-µm effective channel length were fabricated using a single-layer resist process.