Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/.     

低噪声双环路压控振荡器的设计

基于SMIC 65 nm CMOS RF工艺库,设计了一款低噪声差分型双环路压控振荡器。针对振荡器中的延迟单元,引入PMOS交叉耦合正反馈技术,以提高输出波形的摆幅;采用Maneatis负载结构,改善输出波形的对称性;利用次级延迟环路输入MOS管的开关作用,减小振荡周期中PMOS管的沟道热噪声对输出节点的影响,以提高相位噪声性能。后仿真结果表明,在1.2 V电源电压下,可控电压调节范围为0.1~0.7 V时,输出频率调谐范围为3.8~1.63 GHz,在振荡频率为3.8 GHz处的相位噪声为－100.4 dBc/Hz@1 MHz,在1.63 GHz处的相位噪声为－103.5 dBc/Hz@1 MHz,功耗为13.2 mW。     

A very low-power quadrature VCO with back-gate coupling

A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-/spl mu/m triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply.     

Design of a 4.6 GHz high-performance quadrature CMOS VCO using transformer couple

A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral trans-former as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz (7.0%) and the FOM is -189 dB.     

单片低噪声HBT VCO

报道一组单片HBTVCO电路的设计、制作及其测试结果。电路采用HBT作为有源器件，PN结二极管作为变容管。S波段单片VCO的输出功率为0dBm，调谐范围100MHz，在载波频率2．84GHz处，相位噪声为－80dBc／Hz＠100kHz。以C波段单片HBTVCO的输出功率为－10dBm。这些结果表示HBT在微波与毫米波振荡器运用中具有较好的低相位噪声特性。     

变压器耦合的4.6GHz高性能正交CMOS压控振荡器设计

设计一种采用平面螺旋变压器作为耦合终端的CMOS电感电容正交压控振荡器,该正交VCO采用SMIC 0.18 um 数模混合&RF 1P6M CMOS工艺进行了流片验证。测试结果表明：电路在1.8 V电源供电和工作频率为4.6 GHz时,相位噪声为-125.7 dBc/Hz@1MHz,核心直流功耗仅为10 mW。根据时域的输出波形,测量的相位误差大约为1.5°,输出功率约为-2dBm。芯片的工作频率为4.36-4.68 GHz,调谐范围为320MHz(7.0％),电路的优值为-189dB。     

Design and analysis of an ultra-low-power LC quadrature VCO

This paper presents the design of an ultra-low-power LC quadrature VCO (QVCO). It is designed in a single-poly seven-metal 65-nm CMOS process. Several aspects of state-of-the-art QVCO design are addressed, for example tank design and circuit topologies in nano-meter CMOS technology. To minimize power dissipation, an inductor with a high LQ product of 188 nH at 2.4 GHz, and a self-resonant frequency (f _SR ) of 3.8 GHz, was designed. According to post-layout simulations, the power dissipation is below 300 μW at a 0.6 V supply. At this supply, the simulated tuning range and phase noise at 1 MHz offset are 10.3% (2.26–2.5 GHz) and −109.6 dBc/Hz respectively. The phase noise figure of merit (FoM) is better than 182.5 dB at all supply voltages of interest, which is competitive to other state-of-the-art QVCOs.     

Fully balanced current-tunable sinusoidal quadrature oscillator

An integrable current-tunable sinusoidal quadrature oscillator is presented. A current-tunable all-pass filter using a signal-differencing technique is realized as the frequency-selective network. The implementation is fully balanced so as to enable accurate quadrature signals with symmetry. The oscillation frequency is current-tunable over a wide-frequency sweep range of approximately three orders of magnitude. The quadrature signals possess the amplitude matching and the quadrature phase matching of better than 0.004dB and 0.15°, respectively. The maximum useful frequency of oscillation is in excess of 8MHz. Total harmonic distortions are less than 0.5%.     

8-GHz CMOS quadrature VCO using transformer-based LC tank

A fully integrated quadrature VCO at 8 GHz is presented. The VCO is implemented using a transformer-based LC tank in 0.18 /spl mu/m CMOS technology, in which two VCOs are coupled to generate I-Q signals. The VCO is realized employing the drain-gate transformer feedback configuration proposed here. This makes use of the quality factor enhancement in the resonator using a transformer and the deep switching-off technique by controlling gate bias. By turning off switching transistors of the differential VCO core deeply, the phase noise performance is improved more than 10 dB. The measured phase noise values are -110 and -117 dBc/HZ at the offset frequencies of 600 kHz and 1 MHz respectively. The tuning range of 250 MHz is achieved with the control voltage from 0 to 1 V. The VCO draws 8 mA in two differential core circuits from 3 V supply. When the bias voltage goes down to 2.5 V, the phase noise decrease only 2 dB compared to that of 3 V bias. The VCO performances are compared with previously reported quadrature Si VCOs in 5/spl sim/12 GHz frequency range.     

A 1.57-GHz fully integrated very low-phase-noise quadrature VCO

A very low-phase-noise quadrature voltage-controlled oscillator is presented, featuring an inherently better figure of merit than existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit can be lowered. The circuit draws 15 mA from a 2-V supply. The phase noise is -133.5 dBc/Hz at 600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz     

A 0.83-2.5-GHz continuously tunable quadrature VCO

A quadrature VCO with /spl plusmn/50% continuous 0.83-2.5-GHz tuning range is presented. It is based on a core LC-QVCO with /spl plusmn/20% tuning range, a single sideband mixer (SSBM), two frequency dividers and a multiplexer. The circuit has been implemented in a 0.13-/spl mu/m 1.2-V CMOS technology. The additional area with respect to the core LC-QVCO is 100 /spl mu/m/spl times/100 /spl mu/m. Quadrature error is less than 2/spl deg/; the phase noise is less than -120 dBc/Hz @ 1 MHz over the whole tuning range and is mainly due to the LC-QVCO. Spurs are more than 34 dB below the fundamental in the worst case.     

An amplifier linearization method based on a quadrature balanced structure

A quadrature balanced structure is presented for linearizing amplifiers. It works by reducing the most annoying distortion component: the third-order intermodulation. This arrangement has some advantages over the negative feedback method, which is prone to oscillations. It also has advantages over predistortion and feedforward linearization methods, as it is simpler and needs no adjustments. Theoretically, third-order intermodulation products would be totally eliminated when using the proposed arrangement. In practice, it was observed that, even with nonperfectly balanced amplifiers, the third-order intermodulation level was reduced up to 17 dB. The fifth-order intermodulation components were not reduced.     

低相位噪声VCO的设计

设计了一个用于移动通信中继站的低相位噪声压控振荡器(VCO)。该VCO采用了考皮兹结构,谐振器使用LC器件,放大器件使用双极结型晶体管(BJT)。其频率调动范围为730～840 MHz,压控灵敏度为22 MHz/V,输出功率为10.7 dBm。在800 MHz中心频率处,其实测相位噪声分别为-99.42 dBc/Hz@10 kHz,-116.44 dBc/Hz@100 kHz,-135.06 dBc/Hz@1 MHz。提出了一种采用基极低频滤波的办法消除VCO的杂散频率,整个测试频段内观察不到明显的杂散。阐述了VCO相位噪声的主要来源,给出了低噪声VCO的设计方法。理论计算,仿真结果和实物测试取得了一致的结论,对低噪声VCO的设计提供了一定的参考。     

K- and Q-bands CMOS frequency sources with X-band quadrature VCO

Fully integrated 10-, 20-, and 40-GHz frequency sources are presented, which are implemented with a 0.18-/spl mu/m CMOS process. A 10-GHz quadrature voltage-controlled oscillator (QVCO) is designed to have output with a low dc level, which can be effectively followed by a frequency multiplier. The proposed multipliers generate signals of 20 and 40 GHz using the harmonics of the QVCO. To have more harmonic power, a frequency doubler with pinchoff clipping is used without any buffers or dc-level shifters. The QVCO has a low phase noise of -118.67 dBc/Hz at a 1-MHz offset frequency with a 1.8-V power supply. The transistor size effect on phase noise is investigated. The frequency doubler has a low phase noise of -111.67 dBc/Hz at a 1-MHz offset frequency is measured, which is 7 dB higher than a phase noise of the QVCO. The doubler can be tuned between 19.8-22 GHz and the output is -6.83 dBm. A fourth-order frequency multiplier, which is used to obtain 40-GHz outputs, shows a phase noise of -102.0 dBc/Hz at 1-MHz offset frequency with the output power of -18.0 dBm. A large tuning range of 39.3-43.67 GHz (10%) is observed.     

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.     

一种增益与频率成正比的双频段正交压控振荡器

This paper presents a novel dual-band quadrature voltage controlled oscillator(VCO) with the gain proportional to the oscillation frequency.Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration.Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO.The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived.For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with±16%variation over the entire frequency range.The phase noise is -138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and -137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.     

A K-band InGaP/GaAs HBT balanced MMIC VCO

A fully integrated K-band balanced voltage controlled oscillator (VCO) is presented. The VCO is realized using a commercially available InGaP/GaAs heterojunction bipolar transistor (HBT) technology with an f/sub T/ of 60 GHz and an f/sub MAX/ of 110 GHz. To generate negative resistance at mm-wave frequencies, common base inductive feedback topology is used. The VCO provides an oscillation frequency from 21.90 GHz to 22.33 GHz. The frequency tuning range is about 430 MHz. The peak output power is -0.3 dBm. The phase noise is -108.2 dBc/Hz at 1 MHz offset at an operating frequency of 22.33 GHz. The chip area is 0.84/spl times/1.00 mm/sup 2/.     

采用SiGe工艺的低相位噪声压控振荡器

采用0.35μm-BiCMOS-SiCe工艺,设计了单片集成的低相位噪声差动压控振荡器。在电路设计中,需要的在VCO的三个主要性能参数:可调范围、功耗、相位噪声间作出折中的考虑。最终设计的VCO电路工作电压为3.3V,核心电路的功耗为10mV。在1MHz频率偏移下的相位噪声为-114dBc/Hz。振荡频率范围为5.825GHz～5.065GHz,相应的调谐电压为0～2.2V。最后得出结论:0.35μm-SiGe的性能优于0.18μm- CMOS的性能     

5-GHz Low-Phase Noise CMOS Quadrature VCO

A 5-GHz low-phase noise CMOS quadrature voltage controlled oscillator (QVCO) is described. Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate biasing transistors which are switched on and off by the coupling input of each resonator. The proposed QVCO implemented in a 0.13-mum CMOS technology shows 17-dB phase noise improvement from a conventional QVCO with constant tail current sources while the two QVCOs consume the same power of 5.28mW. The phase noise of the proposed QVCO is measured to be -102dBc/Hz and -117dBc/Hz at 100KHz and 1-MHz offset, respectively