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随着器件尺寸的缩小,阻变存储器(RRAM)具有取代现有主流Flash存储器成为下一代新型存储器的潜力。但对RRAM器件电阻转变机制的研究在认识上依然存在很大的分歧,直接制约了RRAM的研发与应用。通过介绍阻变存储器的基本工作原理、不同的阻变机制以及基于阻变存储器所表现出的不同I-V特性,研究了器件的阻变特性;详细分析了阻变存储器的五种阻变物理机制,即导电细丝(filament)、空间电荷限制电流效应(SCLC)、缺陷能级的电荷俘获和释放、肖特基发射效应(Schottky emission)以及普尔-法兰克效应(Pool-Frenkel);同时,对RRAM器件的研究发展趋势以及面临的挑战进行了展望。 相似文献
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针对新型阻变存储器(RRAM)工艺良率不高的问题,提出了一种新型的修复解决方案,该方案基于阻变单元的特殊性能,即初始状态为高阻,经过单元初始化操作过程后转变为低阻。利用这样特性的阻变单元作为错误检测位、冗余单元作为修复位,提出了三种不同的组织结构来实现修复操作。三种结构由于主存储器、检验位存储器及冗余存储器的组织方式不同,达到了不同的冗余存储器利用率。最后,通过数学分析可以证明,该方案在利用了较少冗余存储器的条件下,可以将阻变存储器的错误率普遍降低10~30倍,实现了较好的修复效果。 相似文献
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用热氧化法在空气中加热铜片制备了CuO纳米线(CuO NWs),通过FESEM对纳米线表面进行了观察,并用液体转移法组装成功了一种简单的阻变存储器件。通过I-V测试系统观察到了Cu/CuO NWs/Cu器件表现出了明显的双极型和单极型。最后通过对比高阻态(HRS)和低阻态(LRS)的表面形貌,解释了Cu/CuO NWs/Cu器件的阻变机制。 相似文献
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阻变存储器(RRAM)是一种前景非常好的未来通用存储技术,也是当前国际学术界和工业界研究的热点。主要介绍了存储器外围电路的电路设计,并介绍了阻性存储器外围电路,包括验证电路、写电路、参考模块方案和形式、限流等关键技术的原理,重点讨论了提升复位操作速度,改善高阻值离散性,参考方案的设计和参考单元的组成,用限流实现低功耗操作的方法及其发展趋势。 相似文献
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针对现有阻变存储器中严重影响擦除操作可靠性的"写回"现象,结合测试数据、材料特性及电路原理分析了引起这种现象的主要原因,给出了一种加入"擦除反馈"功能的写电路设计方案。该方案能够对擦除操作进行监控,一旦发现操作完成,立即使用反馈电路关闭写驱动的输出以停止擦除操作,防止"写回"现象。优化后的写电路方案在0.13μm标准CMOS工艺下进行了流片验证。通过测试数据的分析对比,可以看到相比传统的写电路方案,采用文中的电路设计能明显降低"写回失效"的可能,大幅度提高擦除操作的可靠性。 相似文献
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设计了一种应用于3D NAND 存储器的高压生成电路,包括振荡器、时钟生成电路、新型电荷泵及反馈环路。与传统的电荷泵相比,新型电荷泵消除了阈值电压损失与衬底偏置效应,提高了升压效率。通过控制时钟的电压幅度来调节输出电压,减小了输出电压纹波。电路在0.32 μm CMOS工艺模型下进行了仿真验证。结果表明,在3.3 V工作电压下,该电路稳定输出15 V的高压,上升时间为3.4 μs,纹波大小为82 mV,最大升压效率可达到76%。该高压生成电路在各项性能指标之间取得了平衡,其突出的综合性能能满足3D NAND存储器的工作需求。 相似文献
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数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考. 相似文献
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For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration. 相似文献
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NAND flash chips have been innovated from two-dimension (2D) design which is based on planar NAND cells to three-dimension (3D) design which is based on vertical NAND cells. Two types of NAND flash technologies–charge-trap (CT) and floating-gate (FG) are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared. 相似文献
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A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application. 相似文献
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将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。 相似文献
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A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application. 相似文献
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Els Parton 《电子工业专用设备》2007,36(8):11-15
在封装的舞台上,三维集成技术因为在提高电子系统的性能和微型化方面效果卓著而引起重视。目前三维技术的手段一般采用较长的焊线来连接堆叠芯片和基层。新的三维概念仍处在开发阶段,但它将提供更短的互联,更高的互联密度,更低的成本。对于不同的应用,需要有相应且适宜的3D技术。 相似文献
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Three‐dimensional (3D) memories using through‐silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die‐selection method. The conventional die‐selection methods do not result in a high‐enough yields of 3D memories because 3D memories are typically composed of known‐good‐dies (KGDs), which are repaired using self‐contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known‐bad‐die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die‐selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die‐selection method uses three search‐space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die‐selection method can significantly improve the yield of 3D memories in various fault distributions. 相似文献
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Wei Qu Weijun Li Xiaopeng Feng Yuhong He Wanting Pan KeKe Guo Mingbian Li Mingrui Tan Bai Yang Haotong Wei 《Advanced functional materials》2023,33(12):2213955
All-inorganic perovskite cesium lead triiodide (CsPbI3) has attracted much attention among the perovskite family due to its excellent optoelectronic properties and chemical stability. However, the high-temperature crystallization process makes CsPbI3 less compatible with commercially flexible substrates, limiting its application into flexible optoelectronics. Here, a cation of 1-(3-aminopropyl)-2pyrrolidinone (APP) is reported that can form 1D (APP)PbI3 perovskite as templates, and significantly reduce the CsPbI3 black-phase transition energy with a low annealing temperature of 75 °C, which further enables a flexible (APP)PbI3/γ-CsPbI3 (1D/3D) heterostructure photodetector on ITO/PET substrate. A high external quantum efficiency (EQE) greater than 2377% is observed along the orientated 1D/3D heterostructure. The high gain and low noise result in a high specific detectivity (D*) over 1012 Jones under −0.6 V low bias. The optimized device structure brings a high EQE × bandwidth product of 119 kHz under a low driving bias. Due to the high toughness of orientated APP+ ions and the face-connected [PbI3]− chains structure as a strong energy absorber, the flexible photodetector also shows excellent phase stability and impressive flexibility, remaining >90% initial responsivity after over 20 000 times bending with potential flexible imaging application in harsh environments. 相似文献