An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Interactive Content-aware Video Streaming System with Fine Granularity Scalability

Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. From the simulation results, it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity overhead. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures for image/video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing and VLSI design. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A New Efficient Block-Matching Algorithm for Motion Estimation

This paper presents a new full-search block-matching algorithm: Multi-stage Interval-based Motion Estimation algorithm (MIME). The proposed algorithm is a block based motion estimation algorithm that utilizes successive elimination technique. We define two approximate functions, as the upper and lower boundaries of the interval that includes the Conventional distortion metric SAD. Each stage in the proposed algorithm; except for the last stage; incorporates low resolution pixels for the boundary functions calculations. The final stage is a full resolution block matching stage. MIME has a high probability of finding the optimal motion vector at any stage of the algorithm. The proposed algorithm reduces the computational complexity by successively eliminating non-candidate blocks from the search window at each stage. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented in this paper. Simulation results on benchmark video sequences shows that MIME algorithm eliminates almost 88% of the candidate blocks after only two interval based stages. Hanan Ahmed Hosny Mahmoud obtained the B.Sc. of Computer Science from Faculty of Engineering, University of Alexandria in 1986. She obtained her M.Sc. in Computer Science from Faculty of Engineering, University of Alexandria in 1991. She obtained the M.Sc. in Computer Engineering from University of Louisiana at Lafayette in 1999 and the Ph.D. in Computer Engineering from University of Louisiana at Lafayette in 2001. Currently, she is working as an Assistant Professor in the Faculty of Engineering, University of Alexandria. Sumeer Goel received the B. Tech degree in electronics and communications engineering from Punjab Technical University, Punjab, India, in 2001. He received the M.S. degree in computer engineering from University of Louisiana at Lafayette, Lafayette, LA, in 2003 where he is continuing his education towards Ph.D. degree in computer engineering. His research interests are low-power and high noise tolerance VLSI circuit and architecture design for digital signal processing applications. Mohsen Shaaban received his B.S. degree in electrical engineering and communications from the University of Alexandria, Egypt, in 1998. In 2001, he joined the University of Louisiana at Lafayette (ULL) as a teaching and research assistant at the Center For Advanced Computer Studies (CACS), the VLSI Research Lab. He received his M.S. degree in the field computer engineering from ULL in 2003. Currently, he is pursing his Ph.D. degree in the same field. His research interests include Digital VLSI circuit design, CAD tools and Video processing applications. Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures

An energy aware DCT (Discrete Cosine Transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are multiplication free algorithms. One characteristic of the DCT is that upon transformation signal energies are concentrated in only a few coefficients (less than 25%) with the rest (75%) of the coefficients being insignificant and negligible. One can skip the computation of these terms without seriously affecting the output signal quality. Exploiting this idea, we propose a low energy DCT architecture that can achieve 55% savings in the energy dissipation and 28 db in signal quality. In addition, we propose an adaptive energy aware DCT architecture that trades off energy consumption for signal quality. Using this adaptive architecture, we present a study of the effect of coefficient elimination on energy consumption and signal quality.Tarek K. Darwish received the B.S. and the M.S. degrees in computer engineering from the University of Balamand, Lebanon, and the M.S. degree, also in computer engineering, from the University of Louisiana at Lafayette, in 1996, 1998, and 2001, respectively. He received the Ph.D. degree from The Center for Advanced Computer Studies (CACS) at the University of Louisiana in Dec. 2003.From 2000–2003, he has been a research assistant in the CACS, in the VLSI Research group of M. Bayoumi, University of Louisiana. He has one patent pending. Since 2004 he is working as a senior component design engineer with Intel Corporation. His research interests include low power VLSI system design, Digital signal processing with special interest in image and video processing, computer architecture, and CAD-tools.Magdy A. Bayoumi received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, and the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada.Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a faculty member since 1985. He has edited and co-edited three books in the area of VLSI Signal Processing. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. He has one patent pending. His research interests include VLSI design methods and architectures, low power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wideband network architectures.Dr. Bayoumi received the 2003 IEEE Circuit and Systems Education Award, the 1993 Distinguished Professor Award and the University of Louisiana at Lafayette 1988 Researcher of the Year Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VLSI SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he was on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for the technical activities of the IEEE Circuits and Systems Society. He is the general chair of The IEEE International Symposium on Circuits and Systems—ISCAS in 2007. He was the Co-chairman of the Workshop on Computer Architecture for Machine Perception in 1993. He was the General Chairman of the 1994 MWSCAS and Co-chair of 22003 MWSCAS. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication, and he was the chair of the Technical Committee on Signal Processing Design and Implementation. He is a member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette. He is a fellow IEEE.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hard-ware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, in June 2000 and December 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Ching-Yeh Chen was born in Taipei, Taiwan, in 1980. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, in 2002. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His research interests include intelligent video signal processing, global/local motion estimation, scalable video coding, and associated VLSI architectures. Chen-Han Tsai received the B.S. degree in electrical engineering from National Taiwan University in 2002. Now he is working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include face detection and recognition, motion estimation, H.264/AVC video coding, digital TV systems, and related VLSI architectures. Chun-Fu Shen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University in 1996 and 1998, respectively. After two years of military service, he joined VIVOTEK, Inc., Taipei County, Taiwan, in 2000. He developed many video coding systems and IP camera products on DSP platforms and ASICs. His major research interests include JPEG, H.263, MPEG-4, and H.264/AVC coding systems, network camera SOC, and embedded systems. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an instructor (1981–1986), and an associate professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an associate professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a visiting consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is a professor of National Taiwan University. From 2004, he is also the executive vice president and the general director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tau Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He was also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He has served as the associate editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, the associate editor of IEEE Transactions on VLSI Systems since 1999, the associate editor of Journal of Circuits, Systems, and Signal Processing since 1999, and the guest editor of Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology since 2001. Now he is also the associate editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing and the associate editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Awards from ROC Computer Society in 1990 and 1994. From 1991 to 2005, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Outstanding Research Award from National Science Council (NSC) and the Dragon Excellence Award from Acer. He was elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation

In this paper we propose novel high-speed and low-power architecture for the context formation sub-block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 test images, each one 512*512 pixels, gray scale with 8 bit pixels. The proposed architecture incorporates a check unit to detect unnecessary operations in both pass1 and pass2 of the EBCOT block. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture reduces the power consumption about 20.64% and increases the processing speed to about 33.67% with respect to the speedy reference architecture. The proposed architecture has a processing speed close to the parallel mode architectures with almost the same area for serial mode architectures and more power saving. The proposed architecture gathers the basic advantages of the serial and parallel mode implementations in addition to lower power consumption. Ramy E. Aly received the B.S. degree in electrical engineering from University of Alexandria, Egypt, in 1994, and the M.S. degree in electrical engineering from Old Dominion University, VA, in 2001 and M.S. in computer engineering from University of Louisiana at Lafayette, in 2002. He is currently working toward his Ph.D. degree at the Center for Advanced Computer Studies (CACS), University of Louisiana, Lafayette. Since 2001, he has been a Research Assistant with the CACS, in the VLSI Research group of M. A. Bayoumi, University of Louisiana. His research interests include low-power VLSI circuit design, low-power SRAM design, JPEG2000 Architecture and CAD-tools. Magdy A. Bayoumi(S'80-M'84-SM'87-F'99) received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a Faculty Member since 1985. He has edited and coedited three books in the area of VLSI Signal Processing. He has one patent pending. His research interests include VLSI design methods and architectures, low-power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wide-band network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for technical activities of the IEEE Circuits and Systems Society. He was the Cochairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a Member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a Member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a Member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

A secure authentication and billing architecture for wireless mesh networks

Wireless mesh networks (WMNs) are gaining growing interest as a promising technology for ubiquitous high-speed network access. While much effort has been made to address issues at physical, data link, and network layers, little attention has been paid to the security aspect central to the realistic deployment of WMNs. We propose UPASS, the first known secure authentication and billing architecture for large-scale WMNs. UPASS features a novel user-broker-operator trust model built upon the conventional certificate-based cryptography and the emerging ID-based cryptography. Based on the trust model, each user is furnished with a universal pass whereby to realize seamless roaming across WMN domains and get ubiquitous network access. In UPASS, the incontestable billing of mobile users is fulfilled through a lightweight realtime micropayment protocol built on the combination of digital signature and one-way hash-chain techniques. Compared to conventional solutions relying on a home-foreign-domain concept, UPASS eliminates the need for establishing bilateral roaming agreements and having realtime interactions between potentially numerous WMN operators. Our UPASS is shown to be secure and lightweight, and thus can be a practical and effective solution for future large-scale WMNs. Yanchao Zhang received the B.E. degree in Computer Communications from Nanjing University of Posts and Telecommunications, Nanjing, China, in July 1999, and the M.E. degree in Computer Applications from Beijing University of Posts and Telecommunications, Beijing, China, in April 2002. Since September 2002, he has been working towards the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, Florida, USA. His research interests are network and distributed system security, wireless networking, and mobile computing, with emphasis on mobile ad hoc networks, wireless sensor networks, wireless mesh networks, and heterogeneous wired/wireless networks. Yuguang Fang received the BS and MS degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D degree in Systems and Control Engineering from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D degree in Electrical Engineering from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997. From 1987 to 1988, he held research and teaching position in both Department of Mathematics and the Institute of Automation at Qufu Normal University. From September 1989 to December 1993, he was a teaching/research assistant in Department of Systems, Control and Industrial Engineering at Case Western Reserve University, where he held a research associate position from January 1994 to May 1994. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From September 1995 to May 1997, he was a research assistant in Department of Electrical and Computer Engineering at Boston University. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. In May 2000, he joined the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he got early promotion to Associate Professor with tenure in August 2003, and to Full Professor in August 2005. His research interests span many areas including wireless networks, mobile computing, mobile communications, wireless security, automatic control, and neural networks. He has published over one hundred and fifty (150) papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He also received the 2001 CAST Academic Award. He is listed in Marquis Who’s Who in Science and Engineering, Who’s Who in America and Who’s Who in World. Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for IEEE Transactions on Mobile Computing, an Editor for ACM Wireless Networks, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications: Wireless Communications Series, an Area Editor for ACM Mobile Computing and Communications Review, an Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and Feature Editor for Scanning the Literature in IEEE Personal Communications. He has also actively involved with many professional conferences such as ACM MobiCom’02 (Committee Co-Chair for Student Travel Award), MobiCom’01, IEEE INFOCOM’06, INFOCOM’05 (Vice-Chair for Technical Program Committee), INFOCOM’04, INFOCOM’03, INFOCOM’00, INFOCOM’98, IEEE WCNC’04, WCNC’02, WCNC’00 (Technical Program Vice-Chair), WCNC’99, IEEE Globecom’04 (Symposium Co-Chair), Globecom’02, and International Conference on Computer Communications and Networking (IC3N) (Technical Program Vice-Chair).     

Localized algorithms for coverage boundary detection in wireless sensor networks

Connected coverage, which reflects how well a target field is monitored under the base station, is the most important performance metric used to measure the quality of surveillance that wireless sensor networks (WSNs) can provide. To facilitate the measurement of this metric, we propose two novel algorithms for individual sensor nodes to identify whether they are on the coverage boundary, i.e., the boundary of a coverage hole or network partition. Our algorithms are based on two novel computational geometric techniques called localized Voronoi and neighbor embracing polygons. Compared to previous work, our algorithms can be applied to WSNs of arbitrary topologies. The algorithms are fully distributed in the sense that only the minimal position information of one-hop neighbors and a limited number of simple local computations are needed, and thus are of high scalability and energy efficiency. We show the correctness and efficiency of our algorithms by theoretical proofs and extensive simulations. Chi Zhang received the B.E. and M.E. degrees in Electrical Engineering from Huazhong University of Science and Technology, Wuhan, China, in July 1999 and January 2002, respectively. Since September 2004, he has been working towards the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville, Florida, USA. His research interests are network and distributed system security, wireless networking, and mobile computing, with emphasis on mobile ad hoc networks, wireless sensor networks, wireless mesh networks, and heterogeneous wired/wireless networks. Yanchao Zhang received the B.E. degree in computer communications from Nanjing University of Posts and Telecommunications, Nanjing, China, in July 1999, the M.E. degree in computer applications from Beijing University of Posts and Telecommunications, Beijing, China, in April 2002, and the Ph.D. degree in electrical and computer engineering from the University of Florida, Gainesville, in August 2006. Since September 2006, he has been an Assistant Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark. His research interest include wireless and Internet security, wireless networking, and mobile computing. He is a member of the IEEE and ACM. Yuguang Fang received the BS and MS degrees in Mathematics from Qufu Normal University, Qufu, Shandong, China, in 1984 and 1987, respectively, a Ph.D. degree in Systems and Control Engineering from Department of Systems, Control and Industrial Engineering at Case Western Reserve University, Cleveland, Ohio, in January 1994, and a Ph.D. degree in Electrical Engineering from Department of Electrical and Computer Engineering at Boston University, Massachusetts, in May 1997. From 1987 to 1988, he held research and teaching position in both Department of Mathematics and the Institute of Automation at Qufu Normal University. From September 1989 to December 1993, he was a teaching/research assistant in Department of Systems, Control and Industrial Engineering at Case Western Reserve University, where he held a research associate position from January 1994 to May 1994. He held a post-doctoral position in Department of Electrical and Computer Engineering at Boston University from June 1994 to August 1995. From September 1995 to May 1997, he was a research assistant in Department of Electrical and Computer Engineering at Boston University. From June 1997 to July 1998, he was a Visiting Assistant Professor in Department of Electrical Engineering at the University of Texas at Dallas. From July 1998 to May 2000, he was an Assistant Professor in the Department of Electrical and Computer Engineering at New Jersey Institute of Technology, Newark, New Jersey. In May 2000, he joined the Department of Electrical and Computer Engineering at University of Florida, Gainesville, Florida, where he got early promotion to Associate Professor with tenure in August 2003, and to Full Professor in August 2005. His research interests span many areas including wireless networks, mobile computing, mobile communications, wireless security, automatic control, and neural networks. He has published over one hundred and fifty (150) papers in refereed professional journals and conferences. He received the National Science Foundation Faculty Early Career Award in 2001 and the Office of Naval Research Young Investigator Award in 2002. He also received the 2001 CAST Academic Award. He is listed in Marquis Who’s Who in Science and Engineering, Who’s Who in America and Who’s Who in World. Dr. Fang has actively engaged in many professional activities. He is a senior member of the IEEE and a member of the ACM. He is an Editor for IEEE Transactions on Communications, an Editor for IEEE Transactions on Wireless Communications, an Editor for IEEE Transactions on Mobile Computing, an Editor for ACM Wireless Networks, and an Editor for IEEE Wireless Communications. He was an Editor for IEEE Journal on Selected Areas in Communications:Wireless Communications Series, an Area Editor for ACM Mobile Computing and Communications Review, an Editor for Wiley International Journal on Wireless Communications and Mobile Computing, and Feature Editor for Scanning the Literature in IEEE Personal Communications. He has also actively involved with many professional conferences such as ACM MobiCom’02 (Committee Co-Chair for Student Travel Award), MobiCom’01, IEEE INFOCOM’06, INFOCOM’05 (Vice-Chair for Technical Program Committee), INFOCOM’04, INFOCOM’03, INFOCOM’00, INFOCOM’98, IEEE WCNC’04, WCNC’02, WCNC’00 Technical Program Vice-Chair), WCNC’99, IEEE Globecom’04 (Symposium Co-Chair), Globecom’02, and International Conference on Computer Communications and Networking (IC3N) (Technical Program Vice-Chair).     

SOLONet: Sub-optimal location-aided overlay network for MANETs

Overlay networks have made it easy to implement multicast functionality in MANETs. Their flexibility to adapt to different environments has helped in their steady growth. Overlay multicast trees that are built using location information account for node mobility and have a low latency. However, the performance gains of such trees are offset by the overhead involved in distributing and maintaining precise location information. As the degree of (location) accuracy increases, the performance improves but the overhead required to store and broadcast this information also increases. In this paper, we present SOLONet, a design to build a sub-optimal location aided overlay multicast tree, where location updates of each member node are event based. Unlike several other approaches, SOLONet doesn’t require every packet to carry location information or each node maintain location information of every other node or carrying out expensive location broadcast for each node. Our simulation results indicate that SOLONet is scalable and its sub-optimal tree performs very similar to an overlay tree built by using precise location information. SOLONet strikes a good balance between the advantages of using location information (for building efficient overlay multicast trees) versus the cost of maintaining and distributing location information of every member nodes. Abhishek Patil received his BE degree in Electronics and Telecommunications Engineering from University of Mumbai (India) in 1999 and an MS in Electrical and Computer Engineering from Michigan State University in 2002. He finished his PhD in 2005 from the Department of Computer Science and Engineering at Michigan State University. He is a research engineer at Kiyon, Inc. located in San Diego, California. His research interests include wireless mesh networks, UWB, mobile ad hoc networks, application layer multicast, location-aware computing, RFIDs, and pervasive computing. Yunhao Liu received his BS degree in Automation Department from Tsinghua University, China, in 1995, and an MA degree in Beijing Foreign Studies University, China, in 1997, and an MS and a Ph.D. degree in Computer Science and Engineering at Michigan State University in 2003 and 2004, respectively. He is now an assistant professor in the Department of Computer Science at Hong Kong University of Science and Technology. His research interests include wireless sensor networks, peer-to-peer and grid computing, pervasive computing, and network security. He is a senior member of the IEEE Computer Society. Li Xiao received the BS and MS degrees in computer science from Northwestern Polytechnic University, China, and the PhD degree in computer science from the College of William and Mary in 2002. She is an assistant professor of computer science and engineering at Michigan State University. Her research interests are in the areas of distributed and Internet systems, overlay systems and applications, and sensor networks. She is a member of the ACM, the IEEE, the IEEE Computer Society, and IEEE Women in Engineering. Abdol-Hossein Esfahanian received his B.S. degree in Electrical Engineering and the M.S. degree in Computer, Information, and Control Engineering from the University of Michigan in 1975 and 1977 respectively, and the Ph.D. degree in Computer Science from Northwestern University in 1983. He was an Assistant Professor of Computer Science at Michigan State University from September 1983 to May 1990. Since June 1990, he has been an Associate Professor with the same department, and from August 1994 to May 2004, he was the Graduate Program Director. He was awarded ‘The 1998 Withrow Exceptional Service Award’, and ‘The 2005 Withrow Teaching Excellence Award’. Dr. Esfahanian has published articles in journals such as IEEE Transactions, NETWORKS, Discrete Applied Mathematic, Graph Theory, and Parallel and Distributed Computing. He was an Associate Editor of NETWORKS, from 1996 to 1999. He has been conducting research in applied graph theory, computer communications, and fault-tolerant computing. Lionel M. Ni earned his Ph.D. degree in electrical and computer engineering from Purdue University in 1980. He is Chair Professor and Head of Computer Science and Engineering Department of the Hong Kong University of Science and Technology. His research interests include wireless sensor networks, parallel architectures, distributed systems, high-speed networks, and pervasive computing. A fellow of IEEE, Dr. Ni has chaired many professional conferences and has received a number of awards for authoring outstanding papers.     

Performance of Multilayered Video Encoding and Delivery over Lossy Channels Using a Joint Source-Channel Coding Approach

In this paper, the performance of selected error-control schemes based on forward error-control (FEC) coding for H.263+ video transmission over an additive white Gaussian noise (AWGN) channel is studied. Joint source and channel coding (JSCC) techniques that employ single-layer and 2-layer H.263+ coding in conjunction with unequal error protection (UEP) to combat channel errors are quantitatively compared. Results indicate that with appropriate joint source and channel coding, tailored to the respective layers, FEC-based error control in combination with 2-layer video coding techniques can lead to more acceptable quality for wireless video delivery in the presence of channel impairments. Yong Pei is currently a tenure-track assistant professor in the Computer Science and Engineering Department, Wright State University, Dayton, OH. Previously he was a visiting assistant professor in the Electrical and Computer Engineering Department, University of Miami, Coral Gables, FL. He received his B.S. degree in electrical power engineering from Tsinghua University, Beijing, in 1996, and M.S. and Ph.D. degrees in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1999 and 2002, respectively. His research interests include information theory, wireless communication systems and networks, and image/video compression and communications. He is a member of IEEE and ACM. James W. Modestino (S′67- M′73- SM′81- F′87) was born in Boston, MA, on April 27, 1940. He received the B.S. degree from Northeastern University, Boston, MA, in 1962, and the M.S. degree from the University of Pennsylvania, Philadelphia, PA, in 1964, both in electrical engineering. He also received the M.A. and Ph.D. degrees from Princeton University, Princeton, NJ, in 1968 and 1969, respectively. He has held a number of industrial positions, including positions with RCA Communications Systems Division, Camden, NJ; General Electronic Laboratories, Cambridge, MA; AVCO Systems Division, Wilmington, MA; GTE Laboratories, Waltham, MA; and MIT Lincoln Laboratories, Lexington, MA. From 1970 to 1972, he was an Assistant Professor in the Department of Electrical Engineering, Northeastern University. In 1972, he joined Rensselaer Polytechnic Institute, Troy, NY, where until leaving in 2002 he was an Institute Professor in the Electrical, Computer and Systems Engineering Department and Director of the Center for Image Processing Research. He has been responsible for teaching and research in the communication, information and signal processing systems area. His specific research interests include communication in fading dispersive channels; detection, estimation and filtering in impulsive or burst noise environments; digital signal, image and video processing; and multimedia communication systems and networks. In 2002 he joined the Department of Electrical and Computer Engineering at the University of Miami, Coral Gables, FL, as the Victor E. Clarke Endowed Scholar, Professor and Chair. He has held visiting positions with the University of California at San Diego, LaJolla, CA (1981–1982); GE Research and Development Center, Schenectady, NY (1988–1989); and Massachusetts Institute of Technology, Cambridge, MA (1995–1996). Dr. Modestino is a past member of the Board of Governors of the IEEE Information Theory Group. He is a past Associate Editor and Book Review Editor for the IEEE TRANSACTIONS ON INFORMATION THEORY. In 1984, he was co-recipient of the Stephen O. Rice Prize Paper Award from the IEEE Communications Society and in 2000 he was co-recipient of the best paper award at the International Packet Video Conference.     

Blind Stochastic Feature Transformation for Channel Robust Speaker Verification

To improve the reliability of telephone-based speaker verification systems, channel compensation is indispensable. However, it is also important to ensure that the channel compensation algorithms in these systems surpress channel variations and enhance interspeaker distinction. This paper addresses this problem by a blind feature-based transformation approach in which the transformation parameters are determined online without any a priori knowledge of channel characteristics. Specifically, a composite statistical model formed by the fusion of a speaker model and a background model is used to represent the characteristics of enrollment speech. Based on the difference between the claimant's speech and the composite model, a stochastic matching type of approach is proposed to transform the claimant's speech to a region close to the enrollment speech. Therefore, the algorithm can estimate the transformation online without the necessity of detecting the handset types. Experimental results based on the 2001 NIST evaluation set show that the proposed transformation approach achieves significant improvement in both equal error rate and minimum detection cost as compared to cepstral mean subtraction and Znorm. Kwok-Kwong Yiu received a BEng (Hons) degree in 1992 and an MPhil degree in 2000 from the Department of Electronic and Information Engineering, The Hong Kong Polytechnic University. He was a Research Associate at the same institute from 2000 to 2001. He is currently a PhD student and his supervisor is Dr. M.W. Mak. His research interests include speaker verification, neural networks, and channel compensation. Man-Wai Makreceived a BEng (Hons) degree in Electronic Engineering from Newcastle Upon Tyne Polytechnic in 1989 and a PhD degree in Electronic Engineering from the University of Northumbria at Newcastle in 1993. He was a Research Assistant at the University of Northmubria at Newcastle, from 1990 to 1993. He joined the Department of Electronic Engineering at the Hong Kong Polytechnic University as a Lecturer in 1993 and as an Assistant Professor in 1995. Since 1995, Dr. Mak has been an executive committee member of the IEEE Hong Kong Section Computer Chapter. He is currently the chairman of the IEEE Hong Kong Section Computer Chapter. Dr. Mak's research interests include speaker recognition and neural networks. Ming-Cheung Cheung received a BSc (Hons) degree in Information Technology from The Hong Kong Polytechnic University in 2002. Since November 2002, he has been an MPhil student at the Department of Electronic and Information Engineering of The Hong Kong Polytechnic University. His research interests include pattern recognition, neural networks, and fusion techniques for multimodal biometric authentication. Sun-Yuan Kung received his Ph.D. Degree in Electrical Engineering from Stanford University. In 1974, he was an Associate Engineer of Amdahl Corporation, Sunnyvale, CA. From 1977 to 1987, he was a Professor of Electrical Engineering-Systems, the University of Southern California. Since 1987, he has been a Professor of Electrical Engineering, Princeton University. Since 1990, he has served as an Editor-In-Chief of Journal of VLSI Signal Processing Systems. He served as a founding member and General Chairman of various international conferences, including IEEE Workshops on VLSI Signal Processing in 1982 and 1986 (L.A.), International Conference on Application Specific Array Processors in 1990 (Princeton) and 1991 (Barcelona), and IEEE Workshops on Neural Networks and Signal Processing in 1991 (Princeton), 1992 (Copenhagen) and 1998 (Cambridge, UK), the First IEEE Workshops on Multimedia Signal Processing in 1997 (Princeton), and International Computer Symposium in 1998 (Tainan).Dr. Kung is a Fellow of IEEE. He was the recipient of 1992 IEEE Signal Processing Society's Technical Achievement Award for his contributions on “parallel processing and neural network algorithms for signal processing”. He was appointed as an IEEE-SP Distinguished Lecturer in 1994. He received 1996 IEEE Signal Processing Society's Best Paper Award. He was a recipient of the IEEE Third Millennium Medal in 2000. He has authored more than 300 technical publications, including three books “VLSI Array Processors”, (Prentice Hall, 1988) (with Russian and Chinese translations), “Digital Neural Networks”, Prentice Hall, 1993, and “Principal Component Neural Networks”, John Wiley, 1996.     

A Survey on Lifting-based Discrete Wavelet Transform Architectures

In this paper, we review recent developments in VLSI architectures and algorithms for efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic principle behind the lifting based scheme is to decompose the finite impulse response (FIR) filters in wavelet transform into a finite sequence of simple filtering steps. Lifting based DWT implementations have many advantages, and have recently been proposed for the JPEG2000 standard for image compression. Consequently, this has become an area of active research and several architectures have been proposed in recent years. In this paper, we provide a survey of these architectures for both 1-dimensional and 2-dimensional DWT. The architectures are representative of many design styles and range from highly parallel architectures to DSP-based architectures to folded architectures. We provide a systematic derivation of these architectures along with an analysis of their hardware and timing complexities. Tinku Acharya received his B.Sc. (Honors) in Physics, B.Tech. and M.Tech. in Computer Science from University of Calcutta, India, and the Ph.D. in Computer Science from University of Central Florida, USA, in 1984, 1987, 1989, and 1994, respectively. He is currently the Chief Technology Officer of Avisere Inc., Tucson, Arizona, USA. Dr. Acharya is also an Adjunct Professor in the Department of Electrical Engineering, Arizona State University, Tempe, USA. Before joining Avisere, Dr. Acharya served in Intel Corporation (1996–2002), where he led several R&D teams toward development of algorithms and architectures in image and video processing, multimedia computing, PC-based digital camera, reprographics architecture for color photo-copiers, 3G cellular telephony, analysis of next-generation microprocessor architecture, etc. Before Intel, Dr. Acharya was a consulting engineer at AT&T Bell Laboratories (1995–1996), a research faculty at the Institute of Systems Research, Institute of Advanced Computer Studies, University of Maryland at College Park (1994–1995), and held visiting faculty positions at Indian Institute of Technology, Kharagpur. He served as Systems Analyst in National Informatics Center, Planning Commission, Government of India (1988–1990). He collaborated in research and development with Xerox Palo Alto Research Center (PARC), Eastman Kodak Corporation, and many other institutions worldwide. Dr. Acharya is inventor of 88 US patents and 14 European patents. He authored over 80 technical papers and four books—Image Processing: Principles and Applications (Wiley, New Jersey, 2005), JPEG2000 Standard for Image Compression: Concepts, Algorithms, and VLSI Architectures (Wiley, 2004), Information Technology: Principles and Applications (Prentice-Hall India, 2004), and Data Mining: Multimedia, Soft Computing and Bioinformatics (Wiley, 2003). Dr. Acharya is a Fellow of the National Academy of Engineers (India), Life Fellow of the Institution of Electronics and Telecommunication Engineers (FIETE), and Senior Member of IEEE. His current research interests are in computer vision, image processing, multimedia data mining, bioinformatics, and VLSI architectures and algorithms. Chaitali Chakrabarti received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India in 1984, and the M.S. and Ph.D degrees in electrical engineering from the University of Maryland at College Park, USA, in 1986 and 1990 respectively. Since August 1990, she has been with the Department of Electrical Engineering, Arizona State University, Tempe, where she is now a Professor. Her research interests are in the areas of low power embedded systems design including memory optimization, high level synthesis and compilation, and VLSI architectures and algorithms for signal processing, image processing and communications. Dr. Chakrabarti is a member of the Center for Low Power Electronics, the Consortium for Embedded Systems and Connection One. She received the Research Initiation Award from the National Science Foundation in 1993, a Best Teacher Award from the College of Engineering and Applied Sciences, ASU, in 1994, and the Outstanding Educator Award from the IEEE Phoenix section in 2001. She has served on the program committees of ICASSP, ISCAS, SIPS, ISLPED and DAC. She is currently an Associate Editor of the IEEE Transactions on Signal Processing and the Journal of VLSI Signal Processing Systems. She is also the TC Chair of the sub-committee on Design and Implementation of Signal Processing Systems, IEEE Signal Processing Society.     

Energy-aware on-demand routing protocols for wireless ad hoc networks

Energy use is a crucial design concern in wireless ad hoc networks since wireless terminals are typically battery-operated. The design objectives of energy-aware routing are two folds: Selecting energy-efficient paths and minimizing the protocol overhead incurred for acquiring such paths. To achieve these goals simultaneously, we present the design of several on-demand energy-aware routing protocols. The key idea behind our design is to adaptively select the subset of nodes that are required to involve in a route-searching process in order to acquire a high residual-energy path and/or the degree to which nodes are required to participate in the process of searching for a low-power path in networks wherein nodes have transmission power adjusting capability. Analytical and simulation results are given to demonstrate the high performance of the designed protocols in energy-efficient utilization as well as in reducing the protocol overhead incurred in acquiring energy-efficient routes. Baoxian Zhang received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Northern Jiaotong University, Beijing, China in 1994, 1997, and 2000, respectively. From January 2001 to August 2002, he was working with Department of Electrical and Computer Engineering at Queen’s University in Kingston as a postdoctoral fellow. He is currently a research scientist with the School of Information Technology and Engineering (SITE) of University of Ottawa in Ottawa, Ontario, Canada. He has published over 40 refereed technical papers in international journals and conference proceedings. His research interests include routing algorithm and protocol design, QoS management, wireless ad hoc and sensor networks, survivable optical networks, multicast communications, and performance evaluation. He is a member of the IEEE. Hussein Mouftah joined the School of Information Technology and Engineering (SITE) of the University of Ottawa in September 2002 as a Canada Research Chair (Tier 1) Professor in Optical Networks. He has been with the Department of Electrical and Computer Engineering at Queen’s University (1979-2002), where he was prior to his departure a Full Professor and the Department Associate Head. He has three years of industrial experience mainly at Bell Northern Research of Ottawa, now Nortel Networks (1977-79). He has spent three sabbatical years also at Nortel Networks (1986-87, 1993-94, and 2000-01), always conducting research in the area of broadband packet switching networks, mobile wireless networks and quality of service over the optical Internet. He served as Editor-in-Chief of the IEEE Communications Magazine (1995-97) and IEEE Communications Society Director of Magazines (1998-99) and Chair of the Awards Committee (2002-2003). He is a Distinguished Speaker of the IEEE Communications Society since 2000. Dr. Mouftah is the author or coauthor of five books, 22 book chapters and more than 700 technical papers and 8 patents in this area. He is the recipient of the 1989 Engineering Medal for Research and Development of the Association of Professional Engineers of Ontario (PEO), and the Ontario Distinguished Researcher Award of the Ontario Innovation Trust. He is the joint holder of the Best Paper Award for a paper presented at SPECTS’2002, and the Outstanding Paper Award for papers presented at the IEEE HPSR’2002 and the IEEE ISMVL’1985. Also he is the joint holder of a Honorable Mention for the Frederick W. Ellersick Price Paper Award for Best Paper in the IEEE Communications Magazine in 1993. He is the recipient of the IEEE Canada (Region 7) Outstanding Service Award (1995). Also he is the recipient of the 2004 IEEE Communications Society Edwin Howard Armstrong Achievement Award, and the 2004 George S. Glinski Award for Excellence in Research of the Faculty of Engineering, University of Ottawa. Dr. Mouftah is a Fellow of the IEEE (1990) and Fellow of the Canadian Academy of Engineering (2003).     

Statistical Multiplexing based on MPEG-4 Fine Granularity Scalability Coding

Conventional statistical multiplexing methods for MPEG-1/2 programs involve high computationally complex transcoding (decoding and re-encoding) process to convert the original bit-rate into the target bit-rate. To avoid a time-consuming transcoding process, a new statistical multiplexer is proposed to enable content provider to easily convert the bit-rates by exploiting the MPEG-4 fine granularity scalability (FGS) coding scheme. The proposed statistical multiplexer is particularly useful for multiple-program broadcasting applications, including Internet television and video on demand, as well as value-added MPEG-4 video streaming services for DVB and ATSC digital TV systems. The proposed multiplexer mainly includes two parts: the FGS-based frame lag scheme and the optimal bit-plane truncation scheme. The FGS-based frame lag scheme exploits intra- and inter-layer correlations exist in MPEG-4 FGS bit-streams. The optimal bit-plane truncation scheme dynamically truncates enhancement layers of FGS bit-streams under the available bandwidth constraint and the quality/smoothness constraint. Experimental results show that high statistical multiplexing efficiency, inter-program fairness, and intra-program smoothness are achieved by the proposed multiplexer. Portion of this work was presented at Third International Workshop on Digital and Computational Video (DCV2003), USA, November 2002. Xiaokang Yang received B.S. degree from Xiamen University, Xiamen, China, in 1994, M.Eng. degree from the Chinese Academy of Sciences, Shanghai, China, in 1997, and the Ph.D. degree from Shanghai Jiao Tong University, Shanghai, China, in 2000. From September 2000 to March 2002, he worked as a Research Fellow at the Centre for Signal Processing, Nanyang Technological University, Singapore. From April 2002 to October 2004, he was a Research Scientist with the Institute for Infocomm Research (I²R), Singapore. He is currently an Associate Professor of the Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China. His current research interests include scalable video coding, perceptual video processing, video transmission over networks, and digital television. He has published over 60 refereed papers and filed six patents. He is currently a member of Visual Signal Processing and Communications Technical Committee of the IEEE Circuits and Systems Society. He has received awards from A-STAR and Tan Kah Kee foundations (Singapore), and the Best Young Investigator Paper Award at IS&T/SPIE International Conference on Video Communication and Image Processing (VCIP'2003) in perceptual video processing. Nam Ling received a B.Eng. degree in Electrical Engineering from Singapore. He received M.S. and Ph.D. degrees, both in Computer Engineering, from the University of Louisiana at Lafayette, Louisiana, U.S.A. Prof. Ling is currently a full Professor with the Department of Computer Engineering and the Associate Dean (Graduate Studies and Research) for the School of Engineering at Santa Clara University (SCU), California, U.S.A. Prof. Ling is also a Consulting Professor and Honorary Advisor to the National University of Singapore. Prof. Ling has over 120 publications in the fields of video coding, decoder design, video streaming, and systolic arrays. He is the primary author of the book entitled Specification and Verification of Systolic Arrays. Prof. Ling received the Arthur Vining Davis Junior Faculty Fellowship in 1991 and the SCU Outstanding Achievement Award in Teaching, Research, and Service, in 1992. Prof. Ling was named 1999 Researcher of the Year by SCU Engineering. He received the SCU Award for Recent Achievement in Scholarship in 2002 and the President's Special Recognition Award in 2005. He was named IEEE Distinguished Lecturer (Circuits and Systems) for the year 2002-2003. Prof. Ling also received the 2003 IEEE ICCE Best Paper Award. His co-authored fast motion estimation method was adopted into the MPEG/VCEG JVT video international standard in 2005. Prof. Ling served as an Associate Editor for the IEEE Transactions on Circuits and Systems--I in 2002--03. He is currently a Guest Co-editor for the Journal of VLSI Signal Processing Systems. In 1993--1995, Prof. Ling served as the Chair of the IEEE Computer Society Technical Committee (TC) on Microprocessors and Microcomputers. Currently he serves as the Chair-elect for the CASCOM TC (IEEE CAS Society). He is a member in the VSPC TC (IEEE CAS Society) and the DISPS TC (IEEE SP Society). Prof. Ling was the General Chair of the IEEE Hot Chips Symposium in 1995. He served as Program Chair for DCV'02 and SiPS'00. He has been a Track Co-Chair for ISCAS since 2004. Prof. Ling served in program committees, organizing committees, and as session chairs for many IEEE conferences. He holds professional memberships in IEEE, SPIE, and ASEE.