Ridgelet变换及其在图象降噪中的应用

1999年,Stanford大学的E.J.Candes和D.L.Donoho教授提出了信号的一种新的多尺度表示法—Ridgelet变换,它特别适合于具有直线或超平面奇性的二维信号的描述,而且具有较高的逼近精度。随后,M.N.Do和M.Vetterli针对特定大小的离散图象给出了正交有限Ridgelet变换-FiniteRidgeletTransform(FRIT)。该文将FRIT应用于图象降噪,为了说明FRIT的优越性,将Wavelet领域中的多种降噪方法扩展应用到Ridgelet领域。试验结果表明,FRIT比起Wavelet变换更适合描述具有直线边界的图象,而且降噪效果更为明显。     

脊波变换及其在图像处理中的应用

Ridgelet是继小波变换(Wavelet)后提出的一种新型的多尺度分析方法。对于图像中的直线状和超平面的奇异性问题,Ridgelet变换体现了比Wavelet变换更好的处理效果。文中给出了Ridgelet变换的概念及其实现算法,将Ridgelet应用于图像去噪,并和小波去噪加以比较说明其优越性。     

一种高效二维小波分解算法的FPGA实现

针对现有二维提升小波变换实现过程中存在的大量过程数据存储及关键路径延时较长的问题,提出一种直接进行二维变换的VLSI架构.采用Altera公司Cyclone Ⅱ系列FPGA EP2C35F672C6对架构进行实现和验证,在纯计算逻辑下二维小波变换时钟频率可达到157.78 MHz.     

Digital Image Watermark Embedding and Blind Extracting in the Ridgelet Domain

A digital image watermark embedding and extracting algorithm is presented based on the multi-scale Ridgelet Transform （RT） which can efficiently represent image with linear singularities, RT also has directional sensitivity so that among the transformed coefficients the most significant one represents the most energetic direction of straight edges in an image. To get straight edges the digital image with curvilinear edges or texture is partitioned into small pieces, Then these pieces are treated by RT and the most energetic directions of pieces whose energy are greater than some threshold are selected. And eventually the watermarks are embedded in the middle ridgelet subband of the selected directions. Different noises with different SNRs are added into the watermarked image in the experiments and the results are of robustness and transparency.     

VLSI设计中一种新型的功能验证方法

本文在研究了传统的VLSI设计中采用的功能验证方法后,分析了各种方法的特点和不足之处。提出了一种新型的适合于大规模集成电路功能验证的新方法,详细介绍了这种功能验证方法的度量进度机制和验证完备性判断依据,并给出了这种新方法的操作流程和关键点。     

向导滤波器的整数FPGA设计结构

对一种单图像向导滤波器的高性能FPGA设计结构进行了分析,发现其中的均值滤波器存在设计缺陷,据此提出了一种向导滤波器的整数FPGA设计结构。通过改变均值滤波器的数据累加顺序,减少了存储资源的使用,同时以整数数据处理方式实现了向导滤波器中方差和变换系数的计算,并且通过参数调整,可以方便地实现不同大小图像的不同尺寸窗口的向导滤波。在Altera公司Cyclone系列FPGA芯片上进行了综合,实验结果表明,向导滤波整数FPGA结构的处理结果与浮点计算四舍五入取整后的结果相比,最大误差不超过1,同时新结构大幅度降低了硬件资源的使用量,有效提升了数据处理速度,使用EP3C40F484C8芯片综合时,能以高达162fps的速度处理1024×1024的图像,能很好地满足各种图像实时处理要求。     

An architecture for region boundary extraction in raster scan images suitable for VLSI implementation

A novel hardware architecture for extracting region boundaries in two raster scan passes through a binary image is presented. The first pass gathers statistics regarding the size of each object contour. This information is used by the hardware to allocate dynamically off-chip memory for storage of boundary codes. In the second raster pass the same architecture constructs lists of grid-joint codes to represent the perimeter pixels of each object. These codes, referred to variously as crack codes or raster-chain codes in the literature, are later decoded by the hardware to reproduce the ordered sequence of coordinates surrounding each object. This list of coordinates is useful for a variety of shape recognition and manipulation algorithms that utilize boundary information. We present results of software simulations of the VLSI architecture, along with measurements on the coding efficiency of the basic algorithm, and estimates of the overall complexity of a proposed VLSI chip.     

Multistage A2LVQ architecture and implementation for image compression

This paper presents the implementation of two hardware architectures, i.e., A₂ Lattice Vector Quantization (LVQ) and Multistage A₂LVQ (MA₂LVQ), using a Field-Programmable Gate Array (FPGA). First, the renowned LVQ quantizer by Conway and Sloane is implemented followed by a low-complexity A₂LVQ based on a new A₂LVQ algorithm. It is revealed that the implementation requires high number of multiplier circuits. Then the implementation of a low-complexity A₂LVQ is presented. This implementation uses only the first quadrant of the A₂ lattice Voronoi region formed by W and T regions. This paper also presents the implementation of a multistage A₂LVQ (MA₂LVQ) with an architecture built from successive A₂ quantizer blocks. Synthesis results show that the execution time of the low-complexity A₂LVQ reaches up to 35.97 ns. The MA₂LVQ is implemented using both low-complexity A₂LVQ and ordinary A₂ architectures. The system with the former architecture utilizes less logic and register elements by 47%.     

APPlications of Transform and Ant一transform Methods in Remote Sensing Image Processing

遥感图像处理中有许多正变换与逆变换处理，富立叶变换与逆变换、RGB来统与IHS系统之间的彩色空间变换以及主成分变换与逆变换就是典型的变换与逆变换处理技术。灵活地运用这些技术十分重要，分析了这些变换技术的特点，给出了在图像处理中的具休应用实例。     

数字脊波变换的实现与一种改进方法

脊波变换作为一种新的连续空间中函数的多尺度表示方法,其离散变换形式仍然有许多问题有待解决.目前大多将离散脊波变换形式看做Radon变换与小波变换的复合变换形式,进而对其分步进行处理.利用计算机图形学中的Bresenham算法思想,使得在实现Radon变换的过程中提高了变换的效率.与先前的最近邻方法相比,快速准确,并可完全重构.数值实验显示,与Z\\+2\\-p方法实现的脊波变换相比较,利用此方法生成的图像重构、压缩、去噪效果都有显著提高,为进一步的研究工作奠定了基础.     

图像小波分解的FPGA实现

小波分析作为信号处理领域中的一种重要方法,在信号处理、模式分析和图像处理等方面得到了广泛的应用。然而小波变换巨大的运算量却使得它在实时处理领域中的应用受到了限制。本文根据离散小波变换的Mallat算法,提出了一种EPGA实现高速小波分解的方法,设计出的小波变换模块结构清晰而且规则,易于级联,可实现多级变换。同时,,运算精度和处理速度均满足实时图像处理的要求。     

Generalized Discrete Radon Transforms and Their Use in the Ridgelet Transform

We introduce and study a new class of Radon transforms in a discrete setting for the purpose of applying them to the ridgelet and curvelet transforms. We give a detailed analysis of the p-adic case and provide a closed-form formula for an inverse of the p-adic Radon transform. We give conditions for a scaled version of the generalized discrete Radon transform to yield a tight frame, and discuss a direct Radon matrix method for the implementation of a local ridgelet transform. We then study the effectiveness of some types of the generalized Radon transforms in reducing a type of noise known as speckle that is present in synthetic aperture radar (SAR) imagery. Flavia Colonna received the M.A. degree and the Ph.D degree in mathematics from the University of Maryland (College Park) in 1980 and 1985, respectively. She was an assistant professor at the University of Bari (Italy) until she joined the faculty of George Mason University in 1986, where she is currently professor of mathematics. Her research interests include discrete harmonic analysis, integral geometry, potential theory, and classical complex function theory. Glenn R. Easley received the B.S. degree (with honors) and the M.A. degree in mathematics from the University of Maryland, College Park, in 1993 and 1996, respectively, and the Ph.D. degree in computational science and informatics from George Mason University in 2000. Since 2000, he has been working for System Planning Corporation in signal and image processing. His research interests include computational harmonic analysis, wavelet analysis, synthetic aperture radar, deconvolution and computer vision.This revised version was published online in June 2005 with correction to CoverDate     

通用FPGA实验系统的设计与应用

阐述了一种FPGA实验系统的设计思想并较为详细地介绍了PCI接口的开发。实验系统以FPGA为核心,可通过PCI、USB、串行以及网络接口和计算机交换数据。可作为逻辑分析仪、密码协处理器使用,也可用于信息安全、IC设计、嵌入式操作系统等有关的研究、开发和实验。     

基于小波变换的数字水印综述

该文对基于小波变换的数字水印算法做了概要性的介绍。由于其良好的局部性时频分析特性和多分辨率分析,小波变换在图像处理领域有很好的应用效果。基于小波变换的数字水印有突出的抗滤波和压缩攻击的能力,同时由于保留了空域特性,可以和HVS,ROI结合,提高算法鲁棒性。     

VLSI design and implementation of a real-time image segmentation processor

Image segmentation is a crucial part of machine vision applications. In this paper a system to perform real-time segmentation of images is presented. It uses a real-time segmentation VLSI chip that is based on a gradient relaxation algorithm and is designed using the Path Programmable Logic design methodology developed at the University of Utah. The system design considerations, system specifications, and an input/output format for the chip are discussed. The actual design of the chip is given that uses pipeline methodology to achieve real-time performance with a compact VLSI layout. The implementation of the segmentation system is presented and the segmentation chip and the overall system are evaluated with regard to real-time performance and segmentation results.This work was supported in part by Grant ISI-856-0393 from the National Science Foundation.     

A fast digital Radon transform—An efficient means for evaluating the Hough transform

A fast digital Radon transform based on recursively defined digital straight lines is described, which has the sequential complexity of N² log N additions for an N × N image. This transform can be used to evaluate the Hough transform to detect straight lines in a digital image. Whilst a parallel implementation of the Hough transform algorithm is difficult because of global memory access requirements, the fast digital Radon transform is vectorizable and therefore well suited for parallel computation. The structure of the fast algorithm is shown to be quite similar to the FFT algorithm for decimation in frequency. It is demonstrated that even for sequential computation the fast Radon transform is an attractive alternative to the classical Hough transform algorithm.     

Design of an efficient VLSI architecture for non-linear spatial warping of wide-angle camera images

Endoscopic images are subjected to spatial distortion due to the wide-angle configuration of the camera lenses. This barrel type of non-linear distortion should be corrected before these images are subjected to further analysis for diagnostic purposes. An efficient digital architecture suitable for an embedded system which can correct the barrel distortion in real-time is presented in this paper. The theoretical approach of this spatial warping technique is based on least-squares estimation. The images in the distorted image space are mapped onto the corrected image space by using a polynomial mapping model. The polynomial parameters include the expansion coefficients, back-mapping coefficients, distortion centre and corrected centre. Several experiments were conducted by applying the spatial warping algorithm on many endoscopic images. A digital architecture suitable for hardware implementation of the distortion correction technique is developed by mapping the algorithmic steps onto a linear array of processing modules. Each module of a particular unit communicates with its nearest neighbours. The spatial warping architecture implemented and simulated with Altera’s Quartus II software shows an overall computation time of 1.8 ms with 50 MHz clock for an image of size 256 × 192 pixels, which confirms that the spatial warping module could be mounted as a dedicated unit in an endoscopy system for real-time applications.     

Efficient high-performance implementation of JPEG-LS encoder

A new design approach to create an efficient high-performance JPEG-LS encoder is proposed in this paper. The proposed implementation compresses the image data with the lossless mode of JPEG-LS. When the acquisition of precious content (image) is specified to occur in real-time, then lossless compression is essential. Lossless compression is important to critical applications, such as the acquisition of medical images and transmission of high-definition high-resolution images from space (satellite). The contribution of the paper is to introduce an efficient pipelined JPEG-LS encoder, which requires significantly lower encoding time than any other available JPEG-LS hardware or software implementation. The experimental results show that encoding is performed as expected in high-speed, being able to serve real-time applications. This is the first time that a JPEG-LS implementation offers such a high-speed encoding.