Virtual prototyping of embedded microcontroller-based DSP systems

We propose a hardware-software codesign process based on a design methodology called virtual prototyping. With this process, we integrate VHDL models of hardware components with application, control and diagnostic software to rapidly prototype complex, multiboard, embedded microcontroller-based DSP systems. In the virtual prototyping of a demonstration avionics system, in collaboration with Lockheed Sanders, Hughes, and Motorola RASSP teams, we reduced hardware-software integration and system test times from the typical industry figure of 10-24 months to less than a month     

Rapid prototyping for DSP systems with multiprocessors

The authors describe the hardware and software of a system for prototyping digital-signal-processing applications by using commercially available digital-signal processors linked to form multiprocessors. The graphical programming environment makes it easier to program, compile, debug, and test DSP algorithms. The system reduces the cost of application prototyping, making it a feasible step at early design stages. To demonstrate the advantages of their approach, the authors explain how they prototyped a digital audio broadcast system. The complexities encountered highlight the limitations of the system     

嵌入式Linux在数字信号处理系统中的应用研究

结合数字信号处理芯片ADSP-BF561的硬件特性对其上运行的嵌入式Linux系统进行了改进.原有系统在具有双核结构的处理器ADSP-BF561上运行Linux2.6嵌入式操作系统,但系统运行效率低下,不能满足网络多媒体电话应用的实时需求.通过设计合适的系统引导模式、多种程序混合执行模式、线程实现方案、双核通讯方案,解决了嵌入式Linux系统及DSP算法的自动加载,不同编译器执行代码的混合运行,双核的同步与数据传输等问题,实现了嵌入式Linux系统在ADSP-BF561芯片上的高效运行,满足了实时应用需求.     

Asynchronous DSP for low-power energy-efficient embedded systems

This paper presents the design of an asynchronous DSP that is code compatible with the Motorola DSP56000, with the objective of low power and high energy efficiency to extend the lifespan of the batteries in embedded systems embodying the DSP. It features a unified and low-overhead pipeline flush design, a common-case oriented and efficient single-instruction repeating design, and retimed and single-cycle address generation. The asynchronous DSP is implemented using 130 nm CMOS process and is completely standard-cell based. Pre-layout simulation results demonstrate an equivalent speed of 61.5 MIPS and energy dissipation of 54.5 μW/MIPS @ 1.2 V running a Radix 2 FFT benchmark program, and a 30.0% energy reduction compared to the clock-gated synchronous counterpart.     

A flexible DSP core for embedded systems

Cores currently available for ASIC design allow little customization. The authors have developed a parameterized and extensible DSP core that offers system engineers a great deal of flexibility in finding the optimum cost performance ratio for an application     

A cost-effective RISC/DSP microprocessor for embedded systems

Applications in telecommunications or multimedia require a new generation of fast and flexible microprocessors. We present a 32-bit RISC microprocessor with extended functionality for digital signal processing that reduces overall system cost. Due to its optimized design with just 210,000 transistors, this low-cost, medium- to high-performance microprocessor is well suited for a wide range of embedded system applications     

A scalable embedded JPEG 2000 architecture

The latest image compression standard, JPEG 2000 is well tuned for diverse applications, thus raising various throughput demands on its building blocks. Therefore, a JPEG 2000 encoder with the feature of scalability is favorable for its ability of meeting different throughput requirements. On the other hand, the large amounts of data streams underline the importance of bandwidth optimization in designing the encoder. The initial specification, especially in terms of loop organization and array indices, describes the data manipulations and, subsequently, influences the outcome of the architecture implementation. Therefore, there is a clear need for the exploiting support, and we believe the emphasis should lie on the loop level steering. In this paper, we apply loop transformation techniques to a scalable embedded JPEG 2000 encoder design during the architectural exploration stage, considering not only the balance of throughput among different blocks, but also the reduction of data transfer. The architecture is prototyped onto Xilinx FPGA.     

可伸缩增强型DSP定时器的设计与实现

针对高性能多核DSP的需求,设计一种计数宽度和时钟输入可伸缩且功能增强型的定时器,实现定时器不同数据宽度在多种模式下的计数和定时功能。通过对两个32位计数寄存器的组合与分拆,形成多种定时器模式,满足DSP对定时器多种不同功能的要求,提高计数效率;设计实现定时器的看门狗和事件触发功能。实验结果表明,该定时器具有可伸缩、功能强、功耗低等特点。     

Virtual prototyping of mechatronic systems

Mechatronic systems abound in technological fields such as robotics and machine tools industry. Significant advances in dynamic performance of these systems can be achieved provided that mutual interactions of different domains (such as mechanics, electronics, hydraulics and control) are thoroughly understood. Virtual prototyping entails integration of multi-domain dynamic simulation in the design process, in order to reproduce and analyze the effects of design choices on the overall performance. This paper states the requirements of the modeling language and software tool for simulation of mechatronic systems and describes an experience of use of DYMOLA with Modelica language in the simulation of a complete machining center. The model has been successfully validated against experimental results collected on the real machining center.     

Rapid prototyping of computing systems

Pervasive or ubiquitous computing requires the integration of multiple technologies, including software, hardware and human-computer interaction (HCI). To prepare students for this new paradigm in computing, we need multi-disciplinary academic programs and courses. Furthermore, real-world design projects, design processes and team experiences must play a primary role. The course "Rapid Prototyping of Computing Systems" at Carnegie Mellon University (CMU) combines all these elements in a single innovative course offered in multiple departments at CMU. Students learn topics in multiple disciplines and complete an industry-driven, team-based project using a well-defined design process. Although the course prepares students for a wide range of computing applications, the topics and projects focus on pervasive computing.     

Computer-aided prototyping for ASIC-based systems

The use of computer-aided prototyping (CAP) with the RPM Emulation System is described. RPM creates a hardware functional prototype from an ASIC or full-custom chip netlist. It reads the chip netlist and then converts the chip design gates into a prototype design. It then synthesizes the prototype design, obtaining the information it needs to configure the reprogrammable hardware, primarily with partitioning and placement and routing technology. Finally, it physically implements the prototype design by electronically configuring the reprogrammable hardware. RPM includes embedded tools for interactive debugging with access to any internal design node, and a facility for handling quick incremental changes to the design. It is argued that other techniques such as silicon prototyping and manual prototyping are not practical; silicon has a poor debugging ability, and manual prototyping cannot handle large designs. The practical benefits of CAP are discussed     

Modeling discrete event scalable network systems

Scalability in simulation tools is one of the most important traits to measure performance of software. The reason is that today’s Internet is the main instance of a large-scale and highly complex system. Simulation of Internet-scale network systems has to be supported by any simulation tool. Despite this fact, many network simulators lacks support for building large models. In this work, in order to propose a new approach for scalability issue in network simulation tools, a network simulator is developed based on behavior of honeybees and high performance DEVS, modular and hierarchical system theoretic approach. A biologically-inspired discrete event modeling approach is described for studying networks’ scalability and performance traits. Since natural systems can offer important concepts for modeling network systems, key adaptive and emergent attributes of honeybees and their societal properties are incorporated into a set of simulation models that are developed using the discrete event system specification approach. Large-scale network models are simulated and evaluated to show the benefits of nature-inspired network models.     

Securing embedded systems

A top-down, multiabstraction layer approach for embedded security design reduces the risk of security flaws, letting designers maximize security while limiting area, energy, and computation costs.     

基于DSP平台的嵌入式文件系统的开发与研究

在网络多媒体时代,能对大量的多媒体信息进行实时处理的便携式或者嵌入式设备得到了各领域的高度重视。数字信号处理器(DSP)因其具有的高效数字处理能力,在多媒体信号处理和实时设备中获得了大量应用。在多媒体信号处理中同时存在着大容量数据的存储问题。本论文设计实现了基于DSP平台的嵌入式文件系统,从而可以使DSP支持目前通用的大容量存储介质,如IDE硬盘或USB硬盘等,极大的增强了DSP系统的文件访问能力和存储能力。     

Towards scalable synthesis of stochastic control systems

Formal synthesis approaches over stochastic systems have received significant attention in the past few years, in view of their ability to provide provably correct controllers for complex logical specifications in an automated fashion. Examples of complex specifications include properties expressed as formulae in linear temporal logic (LTL) or as automata on infinite strings. A general methodology to synthesize controllers for such properties resorts to symbolic models of the given stochastic systems. Symbolic models are finite abstractions of the given concrete systems with the property that a controller designed on the abstraction can be refined (or implemented) into a controller on the original system. Although the recent development of techniques for the construction of symbolic models has been quite encouraging, the general goal of formal synthesis over stochastic control systems is by no means solved. A fundamental issue with the existing techniques is the known “curse of dimensionality,” which is due to the need to discretize state and input sets. Such discretization generally results in an exponential complexity over the number of state and input variables in the concrete system. In this work we propose a novel abstraction technique for incrementally stable stochastic control systems, which does not require state-space discretization but only input set discretization, and that can be potentially more efficient (and thus scalable) than existing approaches. We elucidate the effectiveness of the proposed approach by synthesizing a schedule for the coordination of two traffic lights under some safety and fairness requirements for a road traffic model. Further we argue that this 5-dimensional linear stochastic control system cannot be studied with existing approaches based on state-space discretization due to the very large number of generated discrete states.     

内嵌ARM9E内核系统级芯片的原型验证方法

随着大容量高速度的FPGA的出现,在流片前建立一个高性价比的原型验证系统已经成为缩短系统级芯片(SoC)验证时间,提高首次流片成功率的重要方法.本文着重讨论了用FPGA建立原型进行验证的流程、优缺点以及常用方法,并结合对一款内嵌ARM9E SoC1所进行的原型验证,说明这一方法在SoC验证中的应用.