A loop-based apparatus for at-speed self-testing

At-speed testing using external tester requires an expensive equipment,thus built-in self-test(BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing.The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead.This paper presents an improved loop-based BIST scheme,in which a configurable MISR (multiple-input signature register)is used to generate test-pair sequences.The structure and operation modes of the BIST scheme are described.The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed.Based on it ,an approach to design and efficiently implement the proposed BIST scheme is developed.Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.     

Exploiting deterministic TPG for path delay testing

Detection of path delay faults requires two-pattern tests.BIST technique provides a low-cost test solution.This paper proposes an approach to designing a cost-effective deterministic test pattern generator(IPG) for path delay testing.Given a set of pre-generated test-pattern generator(TPG) for path delay testing.Given a set of pre-generated test-pairs with pre-determined fault coverage,a deterministic TPG is synthesized to apply the given test-pair set in a limited test time.To achieve this objective,configuable linear feedback shift register(LFSR)structures are used.Techniques are developed to synthesize such a TPG.which is used to generate an unordered deterministic test-pair set.The resulting TPG is very efficient in terms of hardware size and speed performance.SImulation of academic benchmark circuits has given good results when compared to alternative solutions.     

约束输入精简的多扫描链BIST方案

运用有约束的输入精简、LFSR编码与折叠计数器技术,实现了对确定性测试集的压缩与生成.其主要优点是将多种测试方法有机地结合在一起,充分地发挥了各种方法在压缩测试数据方面的优势.与国际上同类方法相比,该方案需要的测试数据存储容量更少,测试应用时间明显缩短,总体性能得到提升;并且能够很好地适应于传统的EDA设计流.     

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability(DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test(BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops(PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design,the test strategies for this case are quite complex,with complicated automatic test pattern generation(ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing(HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.     

Test Time Minimization for Hybrid BIST of Core-Based Systems

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.     

一种选择多个单元的重新播种内建自测试方法

随着集成电路技术的迅速发展,芯片的集成度越来越高,怎样对电路进行有效测试就显得越来越重要。其中内建自测试被认为是解决测试问题有效方法之一。文中提出了一种选择多个单元的重新播种BIST测试方法,实验结果表明该方法可以降低硬件开销。     

构件化软件内建自测试技术研究

目前,构件技术已经在软件工程中广泛使用,同时给软件测试带来了一系列问题.借用硬件自测试的思路,提出了在构件中设置测试点、插装构件接口探针等方法,实现了构件化软件内建自测试.     

减少自反馈测试硬件代价的两种方法

由被测电路自己施加测试向量的内建自测试方法把被测电路视为一种可利用的资源,而不仅仅是被测试的对象.通过将被测电路内部一些节点“反馈”连接到电路的输入端,被测电路可以在由外部加载初始测试向量之后,利用反馈顺序地产生并加载一组测试向量.对这种技术中的分组方法和反馈节点选取方法进行了改进,提出一种附加信息矩阵的面向多个特殊有向图的深度优先公共路径搜索方法和一种贪婪式反馈节点选取方法.对ISCAS85电路和MinTest测试集的仿真实验结果表明,这些方法可以有效减少硬件代价,并提高故障效率.     

用于k测试的BIST测试向量生成器

检测CMOS电路中的开路故障通常需要使用测试向量对。内建自测试(BIST)作为一种有效的测试技术可以大大降低测试开销。本文采用一种具有规则性、模块化和层叠结构的自动控制单元(CA)，来构造产生测试向量对的BIST模块。实验证明，该方法用于瞬态电流测试是有效的。     

一种多核共享测试数据的BIST方案

文中提出了一种新颍的SOC芯片BIST方案。该方案是利用相容技术和折叠技术,将SOC芯片中多个芯核的测试数据整体优化压缩和生成,并且能够实现多个芯核的并行测试,具有很高的压缩率,平均压缩率在94%以上;且结构简单、解压方便、硬件开销低,实验证明是一种非常好的SOC芯片的BIST方案。     

软件内建自测试中的模板库及测试路径分析

软件内建自测试是一种新型的软件测试方法,该文研究了其中的模板库设计和测试路径执行的问题。首先介绍系统的模板库定义及设计,以及它的主要特点,然后介绍了一种将模板库中程序块的执行路径二叉化的方法,使生成的测试用例具有高的路径覆盖率。     

存储器内建自测试技术在芯片设计中的应用

针对SoC芯片中存储器模块的测试问题,在结合设计工具的基础上,提出了存储器的测试结构和方法,并且讨论了存储器模型的应用与调试.     

基于LFSR重播种的测试方法研究

LFSR重播种的测试方法是一种内建自测试方法,存在3种重播种方法,分别是部分动态重播种方法,部分测试向量切分的重播和相容时钟的部分动态重播种方法,这3种方法在硬件开销、编码效率、测试时间方面均有所改进.     

基于伪随机测试的模数混合信号内建自测试法

利用伪随机序列作为测试激励,通过计算输入输出的互相关函数得到K维特征空间,在特征空间的基础上进行分析,判别电路有无故障,实验证明该方法简单可行,且提高了测试的效率和正确性,适用于模拟及混合信号测试,适用于混合信号电路的内建自测试（BIST）。     

并行折叠计数器状态向量选择生成

测试模式生成对集成电路内建自测试(built-in self-test, BIST)的效率具有重要影响.现有的并行折叠计数器(parallel folding counter, PFC)只能实现状态向量(state vector, SV)的顺序折叠计算,导致大量冗余模式产生而限制了其在BIST中的应用.提出一种支持状态向量选择生成的并行折叠计数器,采用固定的初始翻转控制向量(flip control vector, FCV),建立折叠距离与翻转控制向量的内在逻辑关系.通过位替换控制逻辑对折叠距离(folding distance, FD)的译码输出,控制折叠距离最低位对初始翻转控制向量的位替换,产生翻转控制向量;然后与种子向量执行“异或”运算,生成选择的状态向量,其中位替换控制电路可以进行逐级递推设计。理论分析与实验结果表明,与现有方案比较,建议的折叠计数器可以实现n位种子对应的n+1个状态向量的选择生成,显著降低BIST确定性测试生成时间,而硬件开销与现有的并行折叠计数器相当.     

BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count

This paper presents a built-in self-test(BIST) scheme for detecting all robustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator(TPG) generates all n.2^n single-input-change(SIC) orderd test pairs design is universal,i.e.,independent of the structure and functionality of the CUT.A counter that counts the number of alternate transitions at the output of the CUT,is used as a signature analyzer(SA).The design of TPG and SA is simple and no special design-or synthesis-for-testability techniques and /or additional control lines are needed.     

面向存储器核的内建自测试

存储器内建自测试是当前针对嵌入式随机存储器测试的一种经济有效的途径。它实质是BIST测试算法在芯片内部的硬件实现,形成“片上BIST测试结构999作为E-RAM核与芯片系统其他逻辑电路的接口,负责控制功能,实现片上E-RAM的自动测试。根据一个实际项目,本文介绍了MBIST的整体设计过程,并针对测试开销等给出了定量和定性的讨论。     

基于BIST软件测试思想的单元测试框架

BIST是一种成熟的硬件可测性设计的方法,BIST软件测试思想则借用了该技术,它主要包括模板和自治测试部分两大基本结构。在该思想的指导下,整合测试用例、测试点、插装函数、测试报告等测试要素,提出了各个要素的存储或使用方式,以路径覆盖为测试目标,提出了一种BIST软件自测试的测试框架。实践证明,该测试框架有利于BIST软件测试思想的进一步研究和实现。     

基于折叠重排的低功耗BIST技术研究*

为了降低测试功耗,提出一种新的低功耗测试矢量方案,该方案增设了一个可编程的约翰逊计数器。这种技术首先对确定测试矢量进行编码得到LFSR矢量种子,然后对LFSR种子解码、重排得到新的测试矢量。通过ISCAS85实验结果表明,该技术能够改善测试矢量之间的线性相关性,大量减少测试矢量之间的跳变,达到降低功耗的目的。重点介绍了双重编码种子的方法和数据结果分析。     

功耗限制下RTL数据通路非扫描BIST方法的延时分析

可测性设计（DFT）方法广泛应用于数字电路测试中．通过添加测试硬件,用来降低测试的复杂性。但添加测试硬件后,往往会引起电路的延时变大,从而降低电路的性能,甚至引起延时故障。针对寄存器传输级（RTL）数据通路,文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。跟以前的方法相比较,这两个方法取得较短的测试应用时间和较低的测试硬件开销。本文对这两个方法对电路延时的影响进行分析。实验结果表明,在保持同样的测试应用时间和测试硬件开销的前提下,电路的延时有稍微增加。