漫谈FPGA测试基准

对偶尔关心软件的人来说,在鉴定任河软件包时,给FPGA(现场可编程门阵列)—合成软件定出测试基准,尽管似乎是沉闷但却可以有所预见的步骤。透过表面再深入下去,就会发现在一幅幅电影画面的背后,还有更多的戏剧性的情节。     

FPGA实时逻辑除错方案

泰克公司、Altera公司以及First Silicon Solutions(FS2)共同推出能够赋予TLA系列逻辑分析仪对Altera FPGA进行实时除错的软件FPGAView,该软件包将由FS2提供。在采用FPGAView之后,设计工程师将能够简单迅速地对他们的     

FPGA平台的实时图像处理系统设计

本文提出了一种基于FPGA的实时图像处理系统设计方案。介绍了系统硬件结构设计和器件选型方案。并着重介绍了FPGA内部功能模块的设计,使整个处理系统既可支持大数据量的实时传输,又能满足图像数据实时处理的需要。     

基于ATE的FPGA测试

随着集成电路技术的飞速发展,FPGA的应用越来越广泛,其测试技术也得到了广泛重视和研究。文章简要介绍了FPGA的发展及其主要组成部分,提出了一种用ATE对FPGA进行测试的方法和具体测试流程。以一段Xilinx XC3042的真实配置数据为例详细描述了Intel HEX文件格式,以及将其转换成二进制配置码的方法,并介绍了FPGA的配置码格式和配置数据长度的计算方法。然后,以外设配置模式为例,通过XC3042的配置电路原理图和配置时序详细描述了FPGA的配置原理;最后给出了采用ATE（Automatic Test Equipment）-J750对FPGA的配置与测试过程,为FPGA的通用测试提供了一种切实可行的有效方法。     

基于FPGA的实时视频增强

在图像制导应用中,针对雾霾等恶劣天气情况下形成的低对比度图像中目标跟踪稳定性不高的问题,需要对输入的低对比度视频图像进行实时增强预处理.限制对比度自适应直方图均衡算法(Contrast Limited Adaptive Histogram Equalization,CLAHE)是一种增强效果较好、计算简单且易于并行实现的方法,重点研究CLAHE算法架构以及FPGA硬件实现过程,并在Xilinx公司的Virtex-5系列FPGA硬件平台和MODELSIM仿真软件上对算法进行了时序分析、增强效果验证.通过软件仿真和实际平台测试验证,设计正确可行,在实时增强的基础上有效提高目标跟踪精度.     

实时LZW压缩算法的FPGA实现

为降低数据传输的数据量提高传输速度,提出了一种用FPGA实现LZW无损压缩算法的设计方案。字典存储形式是LZW算法中的关键,用内容可寻址存储器构建字典可大大提高字典查询速度。仿真分析了字典容量与压缩率间的关系,使用较少的FPGA资源就能达到较好的压缩效果。     

基于测试系统的FPGA逻辑资源的测试

FPGA在许多领域已经得到广泛应用,其测试问题也显得越来越突出。文章针对基于SRAM结构FPGA的特点,以Xilinx公司的XC4000系列芯片为例,利用检测可编程逻辑资源的多逻辑单元(CLB)混合故障的测试方法,阐述了如何在BC3192V50测试系统上实现FPGA的在线配置以及功能和参数测试。它是一种基于测试系统的通用的FPGA配置和测试方法。     

基于FPGA的实时图像采集系统设计

本文介绍关于干电池缺陷检测系统中图像采集部分的设计。该系统主要包括视频A/D转化芯片Saa7113H、FPGA控制器、存储芯片SRAM。该系统在采集过程中只保留Y分量信息,并且在滤波过程中对图像进行了采样压缩,利用乒乓的操作sram模式使得采集图像和处理图像同时进行,大大的节约了采集时间,为实时性提供了有力保障。     

彩色图像的FPGA实时增强系统实现

为了对彩色图像进行实时增强,本文提出了采用基于插值的分段拉伸算法。首先将彩色RGB图像转换为HSV空间,在该空间,对图像直方图进行基于差值的分段拉伸处理,以达到对图像增强的目的。经过该方法增强后的图像,细节信息更加丰富,图像的清晰度得到了改善,图像的视觉质量也得到了明显提高。经过该算法增强后图像的灰度平均梯度值为直方图均衡化算法的1.95倍。应用现场可编程门阵列(FPGA)为中央处理器,通过并行处理结构及流水线技术,完成图像空间的转换和图像的实时增强算法,简化了系统设计,使处理系统硬件更加紧凑,运行更加可靠。给出了系统主要功能模块的实现方法,经现场调试,可完成每秒30帧×1 024×1 024×24bit数据的处理,与直方图均衡化等传统图像增强算法相比,该算法计算时间缩短了0.807ms。该系统具有集成度高、图像处理速度快和实时性强等特点。     

Application-Dependent Testing of FPGAs

Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage     

BIST-Based Delay-Fault Testing in FPGAs

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testing on the Lattice ORCA 2C and Xilinx Spartan FPGAs.     

Application-Specific Bridging Fault Testing of FPGAs

In this paper, a new technique for testing the interconnects of any arbitrary design mapped into an FPGA is presented. In this technique, only the configuration of logic blocks used in the design is changed, and the structure of the design remains unchanged. The test vector and configuration generation problem is systematically converted to a Boolean satisfiability (SAT) problem, and state of the art SAT-solvers are exploited for test vector and configuration generation. Experimental results on various benchmark circuits show that only two test configurations are required to test for all bridging faults, achieving 100% fault coverage, with respect to the fault list. Moreover, test vector and configuration generation time is less than a second for all benchmark designs.     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.     

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

The objective of this paper is to propose a method to test all the delay faults located in Look-Up-Tables (LUTs) of SRAM-based symmetrical FPGAs. This method is developed in a Manufacturing-Oriented Context (MOT). In the first part of the paper, the timing behavior of the LUTs and the physical defects inducing delay faults in the LUTs are analyzed. Then, the detection conditions to test such delay faults are established and requirements on test vectors are derived. Finally a test configuration scheme and its associated test sequence able to test exhaustively the delay faults in all LUTs of a symmetrical FPGA are proposed.A preliminary version of this work has been presented at the European Test Workshop 2003, in MaastrichtThis revised version was published in March 2005 with corrections to one of the last authors name and the cover date.     

A Carrier-Independent Non-Data-Aided Real-Time SNR Estimator for M-PSK and D-MPSK Suitable for FPGAs and ASICs

We present a channel signal-to-noise ratio (SNR) estimator for $M$-ary phase shift keying (M-PSK) and differential M-PSK. The estimator is non data aided and is shown to have the following advantages: 1) It does not require prior carrier synchronization; 2) the estimator has a compact fixed-point hardware implementation suitable for field-programmable gate arrays and application-specific integrated circuits; 3) it requires only 1 sample/symbol; 4) accurate estimates can be generated in real time; and 5) the estimator is resistant to imperfections in the automatic gain control circuit. We investigate the proposed estimator theoretically and through simulations. In particular, we investigate the required quantization necessary to achieve a good estimator performance. General formulas are developed for SNR estimation in the presence of frequency-flat slow fading, and specific results are presented for Nakagami- $m$ fading. The proposed estimator is then compared with other SNR estimators, and it is shown that the proposed method requires less hardware resources while, at the same time, providing comparable or superior performance.      

Experimental Study on Real-Time Control System Testing

An experimental study on the testing of process control for a real-time control system is presented. Several indexes, such as the capability of system approximation output, the ramp rates, the smoothness and stability of output, and control of temperature overshoot, are selected as performance parameters. With these indexes, the thermal performance of thermal cyelers is validated, analyzed, and monitored. A testing prototype is designed and fabricated as a supplementary instrument for the experimental study. A tracking temperature algorithm with feedforward and feedback controls are also introduced to improve the efficiency of system performance testing.     

一种面向性质的实时系统测试方法

尽管Statecharts在反应式实时系统建模领域获得了广泛应用,基于Statecharts开发的实时软件的测试仍然十分困难.由于引入了时间维,待测系统的行为空间变得非常庞大,使得难以对其进行全面深入测试.本文提出了一种面向性质的实时系统测试方法.首先对UML Statecharts作适当实时扩展,使得扩展后能描述non-trivial时间约束;然后用一种受限实时逻辑描述待测系统的功能特性;在此基础上根据待测性质从系统模型生成有针对性的测试序列.实验表明,在相同测试深度下,面向性质测试比非面向性质测试需要少得多的测试序列.     

Pipeline Reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.     

Pipeline Reconfigurable FPGAs

While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes.