Comments on “A 100-MHz 100 dB operational amplifier withmultipath nested Miller compensation structure” [and reply]

For the original article see ibid., vol. 27, no. 12, 1992. The commenter points out that much of the substance of the aforementioned paper had been published previously and, in some cases, patented. Therefore he wishes proper attribution from the authors. In reply, they point out the basic differences between the two works and disagree with Cherry's complaint     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

A 100-MHz CMOS wide-band IF amplifier

When the data rates of communication systems increase, wideband IF amplifiers are needed. It is also possible to use a single wideband intermediate frequency (IF) amplifier for a radio band with several narrow-band channels of varying strengths. The linearity is then critical, if intermodulation products are not to disturb weak channels. We try to find a topology for this new amplifier application, suitable for integration in a standard CMOS process. To get low distortion, we use an output stage with high linearity, which is further linearized by feedback in a double-nested Miller configuration. A 0.8-μm standard CMOS IF amplifier design with low distortion up to 20 MHz is presented     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply

A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98 dB with 2 dB gain steps and is controlled by 6-bit gain control bits for a 3 V power supply. It has been fabricated in a 0.5 /spl mu/m 15 GHz f/sub T/ Si BiCMOS process and draws 13 mA. The active die area taken up by the circuit is 400 /spl mu/m /spl times/ 1170 /spl mu/m. A noise figure (NF) of 4.9 dB was measured at the maximum gain setting. In addition, an analysis of the bias current generation to provide dB-linear gain control is presented.     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

一种适用于中频接收机的具有75dB动态范围的100MHz带通$\Sigma \Delta$调制器

本文介绍了一款适用于中频接收机的四阶开关电容带通$\Sigma \Delta$调制器,采样频率为100MHz。为优化谐振器的性能,文中提出了考虑运算放大器非理想特性后谐振器的传输函数。本文设计的调制器采用0.13-um标准CMOS工艺,在25MHz附近200KHz信号带宽内测得的SNDR和DR分别为68dB和75dB。调制器工作在1.2V电源电压下,总功耗为8.2mW。     

A 1-GHz bipolar class-AB operational amplifier with multipathnested Miller compensation for 76-dB gain

A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-Ω load is presented. The equivalent input noise voltage is as low as 1.2 nV/√Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a three-stage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz f_T n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm² and has been realized in the bipolar part of a 1-μm BiCMOS process     

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current–voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-$muhbox{m}$ CMOS process, the transconductor occupies 220 $,times,$160 $muhbox{m}^{2}$ active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.      

A 12-dB high-gain monolithic distributed amplifier

By reducing gate and drain line loss associated with the active elements of a distributed amplifier, significant gain improvements are possible. Loss reduction is achieved in a novel monolithic distributed amplifier by replacing the common-source FET's of the conventional design with cascode elements having a gate length of one-quarter micron. A record gain of over 10 dB from 2 to 18 GHz and a noise figure of 4 dB at 7 GHz have been achieved on a working amplifier. Details of the design and fabrication process are described.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-μm CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

A 160-MHz bipolar wide-band IF amplifier

Wide-band intermediate-frequency (IF) amplifiers are needed when the data rates of communication systems increase. A single wide-band IF amplifier can also be used for a radio band with several narrow-band channels of varying strengths. High linearity is then required if intermodulation products are not to disturb weak channels. We have previously reported a highly linear wide-band IF amplifier in a complementary metal-oxide-semiconductor process. Using a similar topology, an npn-only bipolar amplifier with even higher linearity is now presented. The amplifier is fully differential and operates with a 5 V supply, At 20 MHz, 5 V_pp over a 1 kΩ load, the measured total harmonic distortion is just 9.068%     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

A high-voltage monolithic operational amplifier

An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.     

A low-noise NMOS operational amplifier

NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW.     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

A triple-channel micropower operational amplifier

One method of increasing the amount of circuit functions using bipolar devices is to simplify the design of the monolithic chip. This paper describes such a new integrated circuit. The circuit has three independent, micropower, high- gain operational amplifiers on the monolithic chip. Open-loop voltage gain as high as 100 dB has been achieved with a power dissipation of under 300 /spl mu/W. The gain and power dissipation are externally controlled byout board components. Complete performance characteristics along with analysis are presented.