Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10¹²), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.     

面向新型非易失存储的文件系统研究综述

新型非易失存储(NVM)可字节寻址,具有近似内存的低延迟特性以及外存的非易失性,受限于软硬件技术成熟度,目前首先被用于外存.讨论了NVM用于持久性外存所面临的一系列问题,以及管理上的一些挑战;对现有的典型NVM文件系统及其主要特性进行了梳理.归纳起来,这些特性主要围绕降低一致性开销、降低软件栈开销、内存与外存的融合、分布式文件系统、NVM文件系统安全、容错、空间管理几个方面展开.最后,展望了NVM文件系统仍然有待探讨的几个研究方向,包括扩展性问题、虚拟内存与文件系统的有机融合以及分布式文件系统等.     

LASER: Latency-Aware Segment Relocation for non-volatile memory

In this work, we develop Latency-Aware Segment Relocation (LASER) which relocates a subset of segments of binary image to NVRAM to reduce program launch latency. A significant amount of time is spent on loading the binary image to main memory and initializing it. We develop a new system startup mechanism, to reduce the boot time by using selectively relocating read-only sections in NVRAM. We develop a model to determine the set of segments to be loaded into NVRAM given the maximum launch latency constraint and the physical latency of NVRAM. We implement LASER scheme to commercially available embedded systems (S5PC100 and Zynq7020). LASER-enabled systems achieve 54% and 38% reduction in boot time in S5PC100 and Zynq7020 systems, respectively.     

基于纠删码的细粒度云存储调度方案

针对云存储系统中数据获取时延长以及数据下载不稳定的问题,提出了一种基于存储节点负载信息和纠删码技术的调度方案。首先,利用纠删码对文件进行编码存储以降低每份数据拷贝的大小,同时利用多个线程并发下载以提高数据获取的速度;其次,通过分析大量存储节点的负载信息确定影响时延的性能指标并对现有的云存储系统架构进行优化,设计了一种基于负载信息的云存储调度算法LOAD-ALGORITHM;最后,利用开源项目OpenStack搭建了一个云计算平台,根据真实的用户请求数据在云平台上进行部署和测试。实验结果表明,相比于现有的工作,调度算法在数据获取时延方面最高能减少15%的平均时延,在数据下载稳定性方面最高能降低40%的时延波动。该调度方案在真实的云平台环境下能有效地提高数据获取速度和稳定性,降低数据获取时延,达到更好的用户体验。     

基于部件关注DenseNet的细粒度车型识别

针对细粒度车型识别率低,车型区别主要集中在鉴别性部件上以及深度学习不能有效对部件进行关注的问题,提出一种基于部件关注DenseNet(part-focused DenseNet, PF-DenseNet)的细粒度车型识别模型。该模型可以基于细粒度车型的车灯、车标等区分性部件进行有效分类,通过处理层(process layer)对车型部件信息反复加强提取并进行最大池化下采样,获取更多的车型部件信息,然后通过密集卷积对特征通道进一步复用提取,密集卷积前嵌入独立组件(independent component, IC)层,获得相对独立的神经元,增强网络独立性,提高模型的收敛极限。实验结果表明,该模型在Stanford cars-196数据集上的识别准确率、查全率和F₁分别达到95.0%、94.9%和94.8%,高于经典卷积神经网络,并具有较小的参数量,与其他方法相比实现了最高准确率,验证了该车型识别模型的有效性。     

基于模态相关性学习的细粒度分类

针对单模态细粒度分类方法难以区分图像间细微差异的问题,将多模态融合方法引入到细粒度分类任务中,充分利用多模态数据的相关性和互补性,提出了一种基于模态相关性学习的细粒度分类方法。该方法分为两个阶段,首先考虑到图像和文本数据之间的对应关系,利用它们的匹配程度作为约束来进行模型的预训练;接着,加载上一步得到的网络参数,先提取多模态特征,再利用文本特征指导图像特征的生成;最后,基于融合后的特征进行细粒度分类。该方法在UPMC-Food101、MEP-3M-MEATS和MEP-3M-OUTDOORS数据集上进行训练测试,分别达到91.13%、82.39%和93.17%的准确率。实验结果表明,该方法相对于传统的多模态融合方法具有更好的性能,是一种有效的细粒度分类方法。     

面向非易失内存的数据一致性研究综述

在分布式内存系统中,缓存是减少远端内存访问开销的一种有效手段. 然而,单一的缓存一致性保证机制往往不能高效适配不同类型负载的访存特性. 为此,面向分布式异构内存池系统,设计了基于目录和基于广播相结合的混合缓存一致性保证机制. 利用四象限矩阵分析方法,对每个数据对象进行访存模式的判定分析,并为其配置最高效的缓存一致性保证策略,并且可以根据对象访存特征的变化在2 种策略之间动态切换. 实验结果表明,相比使用单一的缓存一致性保证机制,采用可动态配置的混合缓存一致性保证机制可提升分布式异构内存池系统的读和写,性能平均达32.31%和31.20%. 此外,混合的缓存一致性保证机制在客户端数量不断增加时仍然表现出良好的可扩展性.

     

Fine-grained updates in database management systems for flash memory

The growing storage capacity of flash memory (up to 640 GB) and the proliferation of small mobile devices such as PDAs and mobile phones makes it attractive to build database management systems (DBMSs) on top of flash memory. However, most existing DBMSs are designed to run on hard disk drives. The unique characteristics of flash memory make the direct application of these existing DBMSs to flash memory very energy inefficient and slow. The relatively few DBMSs that are designed for flash suffer from two major short-comings. First, they do not take full advantage of the fact that updates to tuples usually only involve a small percentage of the attributes. A tuple refers to a row of a table in a database. Second, they do not cater for the asymmetry of write versus read costs of flash memory when designing the buffer replacement algorithm. In this paper, we have developed algorithms that address both of these short-comings. We overcome the first short-coming by partitioning tables into columns and then group the columns based on which columns are read or updated together. To this end, we developed an algorithm that uses a cost-based approach, which produces optimal column groupings for a given workload. We also propose a heuristic solution to the partitioning problem. The second short-coming is overcome by the design of the buffer replacement algorithm that automatically determines which page to evict from buffer based on a cost model that minimizes the expected read and write energy usage. Experiments using the TPC-C benchmark [S.T. Leutenegger, D. Dias, A modeling study of the TPC-C benchmark, in: Proceedings of ACM SIGMOD, 1993, pp. 22-31] show that our approach produces up to 40-fold in energy usage savings compared to the state-of-the-art in-page logging approach.     

Energy optimization for multi-level cell non-volatile memory using state remapping

Non-volatile Memory (NVM) is emerging as a promising technology to build future main memory or cache. Multi-level cell (MLC) NVM that stores multiple bits in a single cell has been developed in recent years. Different NVM technology has its own writing schemes to store multiple bits, and the amount of write energy varies across different states. For MLC Phase-Change Memory (PCM), the energy consumption of writing intermediate states, ‘01’ and ‘10’, is bigger than that of writing states ‘00’ and ‘11’. For MLC Spin-Transfer Torque Magnetic RAM (STT-MRAM), the energy consumption of flipping the left bit of a 2-bit cell is greater than that of flipping the right bit. To reduce the MLC NVM write energy consumption, we propose an encoding scheme to reduce the amount of intermediate states’ write for MLC PCM and another encoding scheme to decrease the number of the left bit flips for MLC STT-MRAM. The main idea of both schemes is state remapping. We find two minimum write frequency states and remap them to state ‘01’ and ‘10’ respectively for MLC PCM. In addition, for MLC STT-MRAM, we seeks the remapping decision that can minimize the number of the left bit flips and reduces the write of states ‘01’ and ‘10’. The experimental results show that the encoding scheme for MLC PCM saves 5.25% energy on average and the encoding scheme for MLC STT-MRAM saves 12.17% energy on average.     

WOBTree: a write-optimized B+-tree for non-volatile memory

The emergence of non-volatile memory (NVM) has introduced new opportunities for performance optimizations in existing storage systems. To better utilize its byte-addressability and near-DRAM performance, NVM can be attached on the memory bus and accessed via load/store memory instructions rather than the conventional block interface. In this scenario, a cache line (usually 64 bytes) becomes the data transfer unit between volatile and non-volatile devices. However, the failureatomicity of write on NVM is the memory bit width (usually 8 bytes). This mismatch between the data transfer unit and the atomicity unit may introduce write amplification and compromise data consistency of node-based data structures such as B+-trees. In this paper, we propose WOBTree, a Write-Optimized B+-Tree for NVM to address the mismatch problem without expensive logging. WOBTree minimizes the update granularity from a tree node to a much smaller subnode and carefully arranges the write operations in it to ensure crash consistency and reduce write amplification. Experimental results show that compared with previous persistent B+-tree solutions, WOBTree reduces the write amplification by up to 86× and improves write performance by up to 61× while maintaining similar search performance.     

基于多特征组合的细粒度图像分类方法

针对单一特征表示的局限性会导致细粒度图像分类准确度不高的问题,提出了一种基于卷积神经网络（CNN）和尺度不变特征转换（SIFT）的多特征组合表示方法,综合考虑对目标整体、关键部位和关键点的特征提取。首先,分别以细粒度图像库中的目标整体和头部区域训练CNN得到两个网络模型,用来提取目标的整体和头部CNN特征;然后,对图像库中所有目标区域提取SIFT关键点并通过K均值（K-means）聚类生成码本,再将每个目标区域的SIFT描述子通过局部特征聚合描述符（VLAD）参照码本编码为特征向量;最后,组合多种特征作为最终的特征表示,采用支持向量机（SVM）对细粒度图像进行分类。使用该方法在CUB-200-2011数据库上进行实验,并与单一的特征表示方法进行了比较。实验结果表明,该方法与基于单一CNN特征的细粒度图像分类相比提升了13.31%的准确度,证明了多特征组合对细粒度图像分类的积极作用。     

基于细粒度特征融合的部分多模态哈希

多模态数据的指数级增长使得传统数据库在存储和检索方面遇到挑战,而多模态哈希通过融合多模态特征并映射成二进制哈希码,能够有效地降低数据库的存储开销并提高其检索效率.虽然目前已经有许多针对多模态哈希的工作取得了较好的效果,但是仍然存在着3个重要问题:(1)已有方法偏向于考虑所有样本都是模态完整的,然而在实际检索场景中,样本缺失部分模态的情况依然存在;(2)大多数方法都是基于浅层学习模型,这不可避免地限制了模型的学习能力,从而影响最终的检索效果;(3)针对模型学习能力弱的问题已提出了基于深度学习框架的方法,但是它们在提取各个模态的特征后直接采用了向量拼接等粗粒度特征融合方法,未能有效地捕获深层语义信息,从而弱化了哈希码的表示能力并影响最终的检索效果.针对以上问题,提出了PMH-F3模型.该模型针对样本缺失部分模态的情况,实现了部分多模态哈希.同时,基于深层网络架构,利用Transformer编码器,以自注意力方式捕获深层语义信息,并实现细粒度的多模态特征融合.基于MIRFlickr和MSCOCO数据集进行了充分实验并取得了最优的检索效果.实验结果表明:所提出的PMH-F³     

基于层次结构感知的细粒度实体分类方法

针对现有细粒度实体分类（FGET）任务的工作多着眼于如何更好地编码实体和上下文的语义信息,而忽略了标签层次结构中标签之间的依赖关系及其本身的语义信息的问题,提出了一种基于层次结构感知的细粒度实体分类（HAFGET）方法。首先,利用基于图卷积网络（GCN）的层次结构编码器对不同层级标签之间的依赖关系进行建模,提出了基于层次结构感知的细粒度实体分类多标签注意力（HAFGET-MLA）模型和基于层次结构感知的细粒度实体分类实体特征传播（HAFGET-MFP）模型;然后,利用HAFGET-MLA模型和HAFGET-MFP模型对实体上下文特征进行层次结构感知和分类,前者通过层次编码器学习层次结构感知标签嵌入,并与实体特征通过注意力融合后进行标签分类,后者则直接将实体特征输入到层次结构编码器更新特征表示后进行分类。在FIGER、OntoNotes和KNET三个公开数据集上的实验结果表明,与基线模型相比,HAFGET-MLA模型和HAFGET-MFP模型的准确率和宏平均F1值均提升了2%以上,验证了所提方法能够有效提升分类效果。     

基于紧凑型Vision transformer的细粒度视觉分类

Vision transformer(ViT)已广泛应用于细粒度视觉分类中,针对其中存在的大数据量需求和高计算复杂度的问题,提出一种紧凑型ViT模型.首先,使用多层卷积块生成模型输入,保留更多底层信息和归纳偏置,减少对数据量的依赖;然后,使用序列池化技术取消分类令牌的使用,减少计算复杂度;最后,使用部位选择模块和混合损 失函数,进一步提升模型在细粒度视觉分类中的表现.所提出算法在公共数据集CUB-200-2011、Butterfly200、Stanford Dogs、Stanford Cars和NABirds中均进行了实验验证,在只使用少量的数据和计算资源条件下,分别获得了88.9%、87.4%、89.0%、93.4%和88.0%的准确率,训练时间平均比常用的ViT-B_16模型下降了73.8%,同时比TransFG模型下降了93.9%,并且训练过程中的参数量只有这两种模型的1/4左右.实验结果充分表明,所提出的模型较之其他主流的方法在数据量需求和计算复杂度方面具有明显的优越性,可广泛应用于工业过程控制、设备微小故障检测与诊断中.     

面向ASP页面的细粒度资源搜集算法

ASP页面资源搜集是对ASP应用进行访问控制的基础.提出了一种面向ASP页面的细粒度资源搜集算法,能够搜集到ASP页面内的HTML标签和脚本、组件等资源,并给出了算法实现的性能测试和结果分析.该算法为ASP页面资源细粒度的访问控制提供支持,具有较高的查全率和正确率.     

基于词典分类器的细粒度机构名识别

为提高机构名识别精度,满足关系抽取等下游任务的需求,提出分阶段细粒度命名实体识别思想.利用Bert-BiLSTM-CRF模型对机构名进行粗粒度识别,将机构名视为短文本,采用Bert-CNN对构建的机构名词典训练细粒度分类模型,获取机构名的细粒度标签.实验结果表明,提出的分阶段方法在细粒度机构名识别上F1值最佳达到了0....     

深度区域网络方法的细粒度图像分类

目的 在细粒度视觉识别中,难点是对处于相同层级的大类,区分其具有微小差异的子类,为实现准确的分类精度,通常要求具有专业知识,所以细粒度图像分类为计算机视觉的研究提出更高的要求。为了方便普通人在不具备专业知识和专业技能的情况下能够区分物种细粒度类别,进而提出一种基于深度区域网络的卷积神经网络结构。方法 该结构基于深度区域网络,首先,进行深度特征提取任务,使用VGG16层网络和残差101层网络两种结构作为特征提取网络,用于提取深层共享特征,产生特征映射。其次,使用区域建议网络结构,在特征映射上进行卷积,产生目标区域;同时使用兴趣区域（RoI）池化层对特征映射进行最大值池化,实现网络共享。之后将池化后的目标区域输入到区域卷积网络中进行细粒度类别预测和目标边界回归,最终输出网络预测类别及回归边框点坐标。同时还进行了局部遮挡实验,检测局部遮挡部位对于分类正确性的影响,分析局部信息对于鸟类分类的影响情况。结果 该模型针对CUB_200_2011鸟类数据库进行实验,该数据库包含200种细粒度鸟类类别,11 788幅鸟类图片。经过训练及测试,实现VGG16+R-CNN （RPN）和Res101+R-CNN （RPN）两种结构验证正确率分别为90.88%和91.72%,两种结构Top-5验证正确率都超过98%。本文模拟现实环境遮挡情况进行鸟类局部特征遮挡实验,检测分类效果。结论 基于深度区域网络的卷积神经网络模型,提高了细粒度鸟类图像的分类性能,在细粒度鸟类图像的分类上,具有分类精度高、泛化能力好和鲁棒性强的优势,实验发现头部信息对于细粒度鸟类分类识别非常重要。     

Register allocation for write activity minimization on non-volatile main memory for embedded systems

Non-volatile memories are good candidates for DRAM replacement as main memory in embedded systems and they have many desirable characteristics. Nevertheless, the disadvantages of non-volatile memory co-exist with its advantages. First, the lifetime of some of the non-volatile memories is limited by the number of erase operations. Second, read and write operations have asymmetric speed or power consumption in non-volatile memory. This paper focuses on the embedded systems using non-volatile memory as main memory. We propose register allocation technique with re-computation to reduce the number of store instructions. When non-volatile memory is applied as the main memory, reducing store instructions will reduce write activities on non-volatile memory. To re-compute the spills effectively during register allocation, a novel potential spill selection strategy is proposed. During this process, live range splitting is utilized to split certain long live ranges such that they are more likely to be assigned into registers. In addition, techniques for re-computation overhead reduction is proposed on systems with multiple functional units. With the proposed approach, the lifetime of non-volatile memory is extended accordingly. The experimental results demonstrate that the proposed technique can efficiently reduce the number of store instructions on systems with non-volatile memory by 33% on average.     

Thermally actuated buckling beam memory: a non-volatile memory configuration for extreme space exploration environments

A new nano-thermo-mechanical data storage memory is presented which combines two technologies of thermal actuation and buckling beam memory. The memory design is resistant in high radiation environments, making it a reliable memory for spacecraft computer systems. This memory has a data storage density, write/erase speed, and power consumption comparable with current memories. An integrated thermal–mechanical simulation of buckling in nano-mechanical memory is performed to optimize the design parameters. The preliminary system is a bridge with lengths of 20–40 μm, a width of 1 μm, and a thickness of 0.3 μm, in air with a pressure of 5 kPa. The simulation of high energy particle collisions shows radiation does not cause undesired buckling for silicon and silicon carbide bits, which makes the memory applicable for Jovian exploration. Optimization simulations are performed for silicon, silicon carbide, and kapton with various dimensions and actuation heating rates. The current work suggests the length of 20 μm for the bridge to balance the write time and the storage density. Among the beams with the fixed dimensions, kapton shows the fastest write time, with the lowest energy cost. However, high energy electron collision causes buckling in kapton, limiting its use in high radiation applications. The results show that silicon and silicon carbide based systems are viable for use in the extreme radiation environments that will be encountered in future space exploration missions.