A pipelined computer architecture for unified elementary function evaluation

A pipelined computer architecture for rapid consecutive evaluation of several elementary functions (x/y, √x, sin x, cos, x, e^x, ln x, …) using basic CORDIC algorithms is proposed. Continued products iterations of the form (1 + σ_im 2^?k) allow linking n-identical ALU structures to permit n different function evaluations. New algorithms for sin^?1, cos^?1, cot^?1, sinh^?1, cosh^?1 and x^v are developed. Lastly, a new functional efficiency is defined for pipeline architectures which compares favorably to iterative arrays.Index terms—Digital Arithmetic, Pipeline, Unified Elementary Functions, Iterative Algorithms, CORDIC     

The undergraduate curriculum in computer architecture

The subject matter of computer architecture has grown in breadth and depth, forcing teachers to decide what to include and what to omit-and even to justify the course itself. The author makes a strong case for including a broad-based course early in every computing student's program     

Designing computer architecture research workloads

Although architectural simulators model microarchitectures at a high abstraction level, the increasing complexity of both the microarchitectures themselves and the applications that run on them make simulator use extremely time-consuming. Simulators must execute huge numbers of instructions to create a workload representative of real applications, creating an unreasonably long simulation time and stretching the time to market. Using reduced input sets instead of reference input sets helps to solve this problem. The authors have developed a methodology that reliably quantifies program behavior similarity to verify if reduced input sets result in program behavior similar to the reference inputs.     

Embedded computer architecture and automation

The distinct requirements of embedded computing, coupled with emerging technologies, will stimulate system and processor specialization, customization and computer architecture automation     

A universal parallel computer architecture

Advances in interconnection network performance and interprocessor interaction mechanisms enable the construction of fine-grain parallel computers in which the nodes are physically small and have a small amount of memory. This class of machines has a much higher ratio of processor to memory area and hence provides greater processor throughput and memory bandwidth per unit cost relative to conventional memory-dominated machines. This paper describes the technology and architecture trends motivating fine-grain architecture and the enabling technologies of high-performance interconnection networks and low-overhead interaction mechanisms. We conclude with a discussion of our experiences with the J-Machine, a prototype fine-grain concurrent computer.     

Polymorphic-torus architecture for computer vision

A massively parallel fine-grained SIMD (single-instruction multi-data-stream) computer for machine vision computations is described. The architecture features a polymorphic-torus network which inserts an individually controllable switch into every node of the two-dimensional torus such that the network is dynamically reconfigurable to match the algorithm. Reconfiguration is accomplished by circuit switching and is achieved at fine-grained level. Using both the processor coordinate in the torus and the data for reconfiguration, the polymorphic-torus achieves solution time that is superior or equivalent to that of popular vision architectures such as mesh, tree, pyramid and hypercube for many vision algorithms discussed. Implementation of the architecture is given to illustrate its VLSI efficiency     

Teaching design in a computer architecture course

This article presents an approach to teaching computer architecture. This approach introduces design to computer architecture students at an appropriate concise, high level of abstraction. It provides significant student design experiences and a wide coverage of higher level architectural concepts. At Bucknell University we've taught this approach for the past five years to mostly computer science and computer engineering seniors who have had previous courses in computer organization and digital logic     

Challenges in speech-based human–computer interfaces

In this article we present an overview of our current research activities falling into the scope of developing advanced spoken language dialogue systems. These systems need to react flexibly and adaptively depending on the current status of the user and the situation of use. In particular, they require emotion recognition and adaptive dialogue management techniques. Advanced dialogue systems also need proactive capabilities to act as intelligent assistants to their users.     

Naval architecture education and the computer

All practicing naval architects are well aware of the benefits of modern computers in carrying out lengthy routine calculations. What is less often appreciated, however, is that computers now make possible the use of more sophisticated, or more precise, analytical techniques. The purpose of this paper is to show how students of naval architecture are encouraged to use computer at the Naval Academy which strongly supports computer-aided education. There is no attempt in the course on computer application to spell out canned programs. The aim, rather, is to explain the various aspects of the naval architecture calculations and leave it to the individual user to build his own programs to suit his own particular needs. The logic, the precision and the high speed efficiency of the modern computer, when introduced in undergraduate education, can free our profession, not only of the burden of routine work, but of the conservatism of ship design process of the past.     

Software-oriented approaches for teaching computer architecture to computer science students

This paper describes a combination of approaches to provoke deeper comprehension in various topics in computer architecture details to computer science students. It also presents the outcome of this effort. The proposed educational approaches apply to a sequence of two courses on computer architecture and organization. The first course explains basic notions of execution on a processor, as well as hardware details. The tools used are simulation, assembly language and C programming. The second course deals with more advanced matters of computer organization. There, the authors introduced building a simple Linux device driver as a new approach for getting hands-on experience, on issues related to interactions of the operating system kernel with the memory, I/O, peripherals, and bus system components.     

雷达开放系统的计算机体系结构设计

介绍了雷达设计方法的发展,通过分析传统的雷达系统体系架构的不足,引出雷达开放系统的计算机体系结构,指出其在通用性、模块化方面的优势,并给出在这种体系结构下软硬件设计的方案.然后进一步分析作为雷达主控计算机与雷达子系统之间连接的关键--智能控制器的软硬件架构及完成的主要功能.最后介绍了软件系统设计中面向对象方法的应用.     

Parallel computer vision on Polymorphic Torus architecture

Polymorphic Torus is a novel interconnection network for SIMD massively parallel computers, able to support effectively both local and global communication. Thanks to this characteristic, Polymorphic Torus is highly suitable for computer vision applications, since vision involves local communication at the low-level stage and global communication at the intermediate- and high-level stages. In this paper we evaluate the performance of Polymorphic Torus in the computer vision domain. We consider a set of basic vision tasks, namely,convolution, histogramming, connected component labeling, Hough transform, extreme point identification, diameter computation, andvisibility, and show how they can take advantage of the Polymorphic Torus communication capabilities. For each basic vision task we propose a Polymorphic Torus parallel algorithm, give its computational complexity, and compare such a complexity with the complexity of the same task inmesh, tree, pyramid, and hypercube interconnection networks. In spite of the fact that Polymorphic Torus has the same wiring complexity as mesh, the comparison shows that in all of the vision tasks under examination it achieves complexity lower than or at most equal to hypercube, which is the most powerful among the interconnection networks considered.     

An integrated environment for teaching computer architecture

A major problem in teaching computer architecture and organization courses is how to help students make the cognitive leap that connects their theoretical knowledge with practical experience. Numerous researchers involved in computer architecture and organization education have tackled this problem, resulting in a variety of educational tools for computer system simulation. The tools differ greatly in scope, target architecture complexity, simulation level, and user interface. The available educational systems vary in how they handle digital system simulation. They usually offer tools for creating hardware component libraries, viewing simulation results, and conducting statistical analysis of system performance. Available systems range from sophisticated ones, for complex analysis, to simpler ones that are more readily understood by users, both instructors and students. Beyond system simulation, an educational system should support three key objectives. First, it must cover an extensive range of computer architecture and organization topics. Second, it should graphically depict a computer system, from the block level to the register-transfer level. Third, it must provide the means to follow system functions at the program, instruction, and clock cycle levels     

CPU和DRAM加速任务划分方法: 大数据处理中Hash Joins的加速实例

B+树是关系型数据库中用来加速查询的常用索引结构,通过构建平衡树维护关键属性的顺序. 索引提升了数据库查询性能,但其严格的有序关系增加了数据库表的维护开销. 特别是在大数据场景下,数据量激增使得索引查询和维序性能进一步下降. 如何平衡B+树的查询和维序性能,以及在大数据场景下提升索引查询和维序的效率,对提升索引系统性能具有重要意义. 由此设计了一种专用的B+树索引加速系统,对存储和计算进行协同优化,均衡提升索引查询和维序性能. 利用内存突发读写高带宽的特性设计规则的树和节点存储格式以提升内存带宽利用效率,设计高效的同构计算架构和多数据通道以提升索引操作并行度. 同时设计解耦合的子树结构缓解索引维护时的树读写冲突. 实验结果表明,相比于CPU,B+树索引加速系统能够提升系统查询性能超过6.84倍,提升索引维序性能提升超过29.14倍.

     

A new direction for computer architecture research

In the past few years, two important trends have evolved that could change the shape of computing: multimedia applications and portable electronics. Together, these trends will lead to a personal mobile-computing environment, a small device carried all the time that incorporates the functions of the pager, cellular phone, laptop computer, PDA, digital camera, and video game. The microprocessor needed for these devices is actually a merged general-purpose processor and digital-signal processor, with the power budget of the latter. Yet for almost two decades, architecture research has focused on desktop or server machines. We are designing processors of the future with a heavy bias toward the past. To design successful processor architectures for the future, we first need to explore future applications and match their requirements in a scalable, cost-effective way. The authors describe Vector IRAM, an initial approach in this direction, and challenge others in the very successful computer architecture community to investigate architectures with a heavy bias for the future     

Teaching computer aided design in a school of architecture

Architects, in general, have been slower than other building professionals to respond to the challenges offered by the computer. One of the major reasons for this has been the lack of appropriately educated members of the profession to carry out the work required to implement C.A.D. systems. To fulfil this need the Department of Architectural Science at the University of Sydney has, since 1967. offered courses in computer programming and computer applications to undergraduate and post graduate architecture students. This paper reviews the aims of this education programme and discusses some of the peculiar problems encountered when teaching computer methods to architecture students.