CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included     

A novel fully differential telescopic operational transconductance amplifier

w rate are also enhanced.     

一种新的套筒式全差分跨导放大器设计

A novel fully differential telescopic operational transconductance amplifier （OTA） is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18 μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.     

Low-distortion low-voltage operational transconductance amplifier

A new operational transconductance amplifier (OTA) is proposed, which is based on the flipped voltage follower and source degeneration techniques. The OTA is simulated in a standard TSMC 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show that the total harmonic distortion of the proposed OTA is less than 1% up to 0.85 Vp-p.     

Large-signal subthreshold CMOS transconductance amplifier

A folding architecture for a subthreshold CMOS transconductance amplifier is described. Good linearity is obtained for an extremely large differential input voltage, without loss in the common-mode voltage range. Theoretical noise analysis indicates a 6 dB improvement in the dynamic range compared to a simple single-pair MOS implementation. A prototype has been fabricated in a 2 μm CMOS process, and experimental results are presented     

Low distortion CMOS transconductance amplifier

A novel low distortion CMOS linearized transconductor circuit is developed for analogue signal processing. The circuit gives a very low distortion level and a wide linearity range when compared with other reported topologies. Simulation results based on using the 0.5 µm CMOS process show that this approach gives an exceptional linearity and an excellent performance.     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

A CMOS multi-gain transconductance amplifier and its applications

Transconductance amplifier (g_m) based circuits are attractive due to their inherent programmability features. Single output g_m’s are often replaced by multi-output g_m’s to reduce the number of active devices for a given application. However, this usually results in losing the circuit programmability features. This work shows that this problem can be circumvented through adopting a new programmable multi-gain g_m. The advantages of the proposed multi-gain g_m are demonstrated using two filter design examples. They show that the proposed multi-gain g_m reduces the number of active devices by two-third compared with their single output g_m based counterparts while maintaining their versatile programmability characteristics. Experimental results obtained from a 0.18 μm CMOS process for one of the applications are provided.     

A high-swing CMOS telescopic operational amplifier

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-μm CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of ±2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies     

A high performance CNFET-based operational transconductance amplifier and its applications

High performance electronic systems face several challenges in driving innovative integrated circuits when the internal transistors are scaled down below 45 nm. Carbon nanotube field effect transistors (CNFETs) are considered as excellent candidates for building energy-efficient electronic systems in the near future, due to their unique characteristics such as ballistic transport, scalability, and better channel electrostatics. In this paper, a new high performance operational transconductance amplifier (OTA) based on 32 nm CNFET devices is presented. The proposed OTA maintains a highly linear wide continuous tuning range and a wide frequency response range, enabled by splitting the linear voltage-to-current conversion and tuning two different blocks. As an application, a universal second-order transconductance-capacitor (G _m  ? C) filter realized using the OTA is introduced. Simulation results show that the CNFET-based OTA offers very a low current consumption of 2.35 μA from a ± 0.9 V power supply, achieves a bandwidth of 9.5 MHz, and has an input dynamic range of ± 0.2 V.     

A new CMOS design of high transconductance current follower transconductance amplifier and its applications

In this work, a new CMOS implementation of high transconductance current follower transconductance amplifier (CFTA) is proposed. The proposed CFTA uses current starving technique along with an auxiliary unit (AU) to enhance transconductance performance. The cross-drain-coupled MOSFETs are also used in AU which further enhances transconductance of proposed circuit. The proposed CFTA provides higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA provides transconductance of 11.3 mS, dissipates 1.8 mW power and operates at?±?0.6 V supply voltage. A current mode third order quadrature oscillator and biquad filter have been designed and simulated, to validate the performance of proposed circuit. The workability of proposed CFTA and its applications have been verified by using Cadence virtuoso schematic composer with TSMC 0.18 µm process parameters.     

一种超宽带伪差分跨导放大器

提出了一种超宽带伪差分运算跨导放大器.该放大器通过共模前馈和共模反馈方法使得运算跨导放大器单元具有更为简单的电路结构,易于设计验证并能够稳定工作在较高频率.以该放大器作为单元电路,可以实现截止频率到达百兆赫兹的高频连续时间滤波器,并作为中频滤波器用于射频接收机中.     

A CMOS differential difference operational mirrored amplifier

Design of a high-performance differential difference operational mirrored amplifier is presented. The proposed circuit is useful for continuous-time analog signal processing. The circuit is developed using folded cascode amplifier and the floating current source. Several applications including grounded resistor, voltage amplifier, grounded inductor and oscillator circuit are presented. Simulation results for the DDOMA circuit and its applications are given.     

An improved frequency compensation technique for CMOS operational amplifiers

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

一种亚阈值有源共源共栅补偿运算放大器

针对低压低功耗高增益高带宽应用背景的运算放大器,提出一种新型亚阈值有源共源共栅补偿(SACC)运算放大器。通过使用亚阈值跨导提升辅助放大器,以非常低的功耗成本改善整体电路的带宽,同时有效地减小补偿电容的数值,且输出级采用动态前馈结构,显著提升电路摆率。当驱动10 pF容性负载时,放大器的补偿电容仅需60 fF即可实现稳定,从而大大减小了放大器的版图面积。提出的放大器在28 nm CMOS工艺下设计并验证,并且当驱动10 pF的容性负载时,仿真结果表明,在0.9 V电源电压下,可实现69.5 dB的直流增益和13.3 MHz的增益带宽积,且功耗仅为4.5μW。此外,提出的放大器与现有的方案相比较具有更好的品质因数(FOM)。     

High slew-rate CMOS operational amplifier

A 0.8 /spl mu/m CMOS operational amplifier configuration with a slew rate in excess of 2 V/ns and a unity gain bandwidth of 55 MHz with a load capacitance of 15 pF is proposed. This employs a dynamic technique that turns on a large current source when the rate of change of input is larger than a pre-decided value.