共查询到20条相似文献,搜索用时 140 毫秒
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提出了一种新的适用于突发摸式的QPSK全数字快速同步方案,该方案采用DPLL结构实现。重点介绍了载波恢复和位时钟恢复环路的原理和算法,并进行了仿真。仿真结果证实了算法的可行性,同前馈估计的方案相比,由于算法简单,因而更易于硬件实现。 相似文献
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介绍了积分级联梳状滤波器的设计和实现,并运用Verilog语言在FPGA上进行了仿真,给出了仿真结论,实验结果表明CIC滤波器结构简单,该方案切实有效和可行. 相似文献
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软件无线电信道化发射机及其FPGA实现 总被引:1,自引:0,他引:1
首先建立了信道化软件无线电发射机数学模型,并对该模型进行了算法优化,在对现行的硬件实现方案比较分析后,提出了用FPGA(现场可编程门阵列)实现该发射机结构的简单有效方法,用Altera公司的仿真软件QUARTUSⅡ4.0和IP Core对其实现进行了仿真,比较发现该仿真结果与MATLAB给出的理论仿真结果一致.这种信道化发射机能同时发射整个处理带宽内所有信道上的信号,具有很高的运算效率,且结构简单,可行性强. 相似文献
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介绍DVB数字视频广播条件接收系统中的CSA通用加扰算法,分析了CSA算法结构及块加密和流加密的流程,提出了该算法的硬件实现方案,并简化了块加密中的子密钥生成,最后在FPGA上实现该方案,通过仿真和实际码流加扰测试,验证了该硬件实现方案的正确性. 相似文献
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MEMS毫米波滤波器的设计与制作 总被引:1,自引:1,他引:0
开展了一种基于MEMS工艺的毫米波带通滤波器结构设计和工艺实现,该滤波器结构采用高阻硅作为衬底材料的薄膜支撑结构,选用平行耦合滤波器形式,使用HFSS分析软件对该结构进行了模拟仿真。设计了中心频率为35.0GHz、带内损耗为2.2dB、30dB抑制带宽为2.2GHz的MEMS毫米波滤波器。给出了一套能降低毫米波损耗的MEMS毫米波带通滤波器工艺流程方案,并针对该工艺流程方案进行了关键参数的工艺误差仿真,实现了MEMS毫米波滤波器的工艺制作和测试。测试结果表明,获得的毫米波滤波器的测试结果与仿真结果比较接近。 相似文献
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In this paper, we proposed a FPGA implementation architecture for SVM classifier. The architecture is based on the proposed Shared Dot Product Matrix (SDPM) method which computes and stores the dot product of all training data before SVM searching process. We implemented the proposed method by software simulation and hardware implementation. The software simulation of SDPM method achieves twice the speed of LIBSVM, which is one of the most popular SVM implementation libraries. This acceleration mainly results from the reduction of repeat Kernel function calculation. Then the hardware software collaboration architecture for SDPM is also proposed in this paper. Results show that the proposed architecture achieves approximately 30 times faster searching speed compared with LIBSVM. 相似文献
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单片机仿真的设计与实现 总被引:2,自引:0,他引:2
本文主要论述了S4系统中uPD78k014单片机仿真软件的设计思想和部分实现技术,介绍了单片机仿真软件的体系结构及软件编程实现手段,并以时钟发生器和中断机构为例阐明了编程实现过程中一些实现方法。 相似文献
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文章阐述了虚拟现实和系统仿真技术在虚拟仿真训练系统中的应用,从软件复用的角度分析了研究虚拟仿真训练系统开发架构的重要性和现实意义。提出了面向图形对象的系统仿真模型,并定义了开发虚拟仿真训练系统的软件框架。利用此软件框架实现了某型飞机的虚拟仿真训练系统,开发了面向图形对象的系统仿真模型的设计和解算工具,为实现虚拟仿真训练系统提出了一种新的解决方案。 相似文献
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Hassoun S. Kudlugi M. Pryor D. Selvidge C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(2):278-287
The availability of millions of transistors on a single chip has allowed the creation of complex on-chip systems. The functional verification of such systems has become a challenge. Simulation run times are increasing, and emulation is now a necessity. Creating separate verification environments for simulation and emulation slows the design cycle and it requires additional human efforts. This paper describes a layered architecture suitable for both simulation and emulation. The architecture uses transactions for communication and synchronization between the driving environment (DE) and the device under test (DUT). Transactions provide synchronization only as needed and cycle and event-based synchronization common in emulators. The result is more efficient development of the DE and 100% portability when moving from simulation to emulation. We give an overview of our layered architecture and describe its implementation. Our results show that, by using emulation, the register-transfer level (RTL) implementation of an industrial design can be verified in the same amount of time it takes to run a C-based simulation. We also show two orders of magnitude speeds up over simulations of C and RTL through a programming language interface 相似文献
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大点数FFT运算是数字信号处理中关键技术环节,本文提出一种大点数FFT运算基的实现,该实现是根据[1]中所提出的算法,结合寄存器阵列模块和重排序模块,实现FFT运算基模块内部的数据传输和模式切换,以基4与基2为模块中的基本运算单元构成大点数的FFT运算基,在控制电路配合下实现快速傅里叶变换。该实现通过面向寄存器级的Simulink仿真模型,验证本文所设计模块功能的正确性和可行性,为基于大点数的FFT运算指出了一种实现方法。 相似文献
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A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5-μ technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL2 of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architecture's behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard 相似文献