一种适用于SoC的瞬态增强型线性稳压器

为满足SoC系统负载快速变化的要求,提出了一种新型摆率增强型片上LDO系统。通过增加有效的内部检测电路,使LDO的功率管栅极电压可以快速地响应输出负载跳变,提高电路响应速度。采用中芯国际40 nm CMOS工艺模型,对电路进行仿真。仿真结果表明,当LDO的负载电流以100 mA/μs跳变时,电路的最大上冲电压为110 mV,下冲电压为230 mV,恢复时间分别为1.45 μs和1.6 μs。同时,在2 V电源电压下,电路的静态电流只有42 μA。     

一种带瞬态响应增强的无电容型LDO

在传统无电容型LDO的基础上,设计了一种带瞬态增强的无电容型LDO。采用频率补偿方案,有效减小所需的片上补偿电容,节约了芯片面积。采用了过冲/下冲检测电路,用于检测负载瞬间变化时输出电压的变化,通过调节功率管栅极电压,提升了LDO的瞬态响应速度。采用0.13 μm标准CMOS工艺,对设计的瞬态增强无电容型LDO进行仿真验证。结果表明,片上补偿电容为2 pF时,系统静态电流为30 μA,当负载在1 μs内从1 mA变化到50 mA时,输出电压过冲为88 mV,下冲为50 mV,与不带过冲/下冲检测电路的LDO相比,分别提高了56%和54%。     

一种快速瞬态响应的无片外电容型LDO

设计了一种快速瞬态响应的无片外电容型LDO。采用高增益高带宽的超级跨导结构(STC)的误差放大器,利用动态偏置技术与电容耦合技术,极大地增强了摆率。引入额外的快速响应环路,进一步提升了瞬态响应速度。基于0.18 μm CMOS工艺进行设计。结果表明,该LDO的最低供电电压为1 V,漏失电压仅为200 mV,可提供最大100 mA的负载电流,能在最大输出电容为100 pF、最低负载为50 μA的条件下保证电路稳定。负载电流在0.5 μs内由50 μA跳变至100 mA时,LDO输出导致的过冲电压和下冲电压分别为200 mV和306 mV。     

适用于高频开关芯片的快速瞬态响应LDO设计

设计了一种片外大电容快速瞬态响应低压差线性稳压器。该LDO电路基于跨导线性结构设计,在输出级引入推挽结构,有效地减小过冲的幅值和恢复时间,提高了LDO的瞬态响应速度;利用浮动缓冲器驱动功率管,有效地提高了LDO的电流效率;采用动态零点补偿技术,保证了LDO在全负载范围内的环路稳定性。该LDO电路基于0.35μm BCD工艺设计与仿真验证。结果表明,在1.2 V~3 V输入电压范围,LDO的输出电压为1 V,静态电流约为50μA,可提供0~300 mA的负载。在上升下降沿为500 ns、幅度为300 mA、轻载持续时间为50μs的负载瞬态跳变下,过冲和下冲均小于20 mV。电路满足高频负载跳变的应用需求。     

一种快速瞬态响应无片外电容LDO

针对无片外电容LDO,在误差放大器与功率管之间添加缓冲器,采用频率补偿的方法,提高了环路稳定性。通过检测负载瞬态变化引起的误差放大器输出电压变化,增加对功率管栅极电容的充放电电流,提升了系统的快速瞬态响应能力。基于TSMC 0.18 μm标准CMOS工艺,设计了一种输入电压范围为1.92~3.60 V、输出电压为1.8 V的LDO。结果表明,负载在1 μs内从0变化到100 mA时,输出最大下冲电压为37.2 mV,响应时间为1.12 μs;负载在1 μs内从100 mA变化到0时,输出最大过冲电压为40.1 mV,响应时间为1.1 μs。     

一种无片外电容的快速响应FVF-LDO北大核心

提出了一种无片外电容、快速瞬态响应、宽输入电压范围的低压差线性稳压器(LDO)。该电路基于翻转电压跟随器(FVF)结构，不需额外增加辅助电路，仅使用两个电容作为检测模块，以动态调整瞬态响应，能够弥补传统LDO集成度低、面积大、功耗高、瞬态响应差的不足。电路基于TSMC 180 nm CMOS工艺。仿真结果表明，该LDO的压差为200 mV,静态电流为36μA,输入电压范围为2～4 V,低频时PSRR为-59 dB。在30 pF负载电容、0～10 mA负载电流、150 ns阶跃时间条件下，产生的上冲电压为50 mV,下冲电压为66 mV,瞬态电压恢复时间为300 ns。     

一种采用电压检测器的无片外电容FVF-LDO

提出了一种基于翻转电压跟随器(FVF)的无片外电容低压差线性稳压器(LDO)。采用电压检测器来检测输出电压,大幅改善了瞬态响应,克服了常规LDO面积大、需要使用片内大电容的缺点,仅消耗了额外的静态电流。该LDO采用90 nm CMOS工艺进行设计与仿真,面积为0.009 6 mm²,输入电压为1.2 V,压差为200 mV。结果表明,在50 pF负载电容、3～100 mA负载电流、300 ns跃迁时间的条件下,产生的上冲电压为65 mV,瞬态恢复时间为1 μs,产生下冲电压为89 mV,瞬态恢复时间为1.4 μs,且将负载调整率性能改善到0.02 mV/mA。     

一种缓冲器阻抗动态调整的LDO

提出了一种缓冲器阻抗动态调整的LDO结构。采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响。该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能。基于TSMC 0.18 μm 3.3 V CMOS工艺进行设计,该LDO的输出电压为1.8 V,压差电压为0.2 V,最大输出电流为100 mA。仿真结果显示,LDO的静态电流只有5 μA,当负载电流在10 ns内从0 mA跳变到100 mA时,输出欠冲和过冲电压分别为88.2 mV和34.8 mV。     

基于双环调节的快速瞬态响应无片外电容LDO

基于双环路控制构建推挽结构,增强了功率管栅端的摆率,改善了无片外电容LDO的瞬态响应。此外,结合A类复合放大器特性,降低了功率管栅端阻抗,有利于提升LDO的频率稳定性。该LDO输入电压范围为2.0~3.5 V,输出电压为1.8 V,最大负载电流为100 mA。当负载电流在1 μs内从100 μA跳变到100 mA以及从100 mA跳变到100 μA时,最大下冲电压为128 mV,最大上冲电压为170 mV,建立时间分别为2.5 μs和2.4 μs,电路工作时消耗的静态电流仅为12.6 μA。     

一种快速瞬态响应LDO的设计与实现

设计了一种快速瞬态响应LDO。采用缓冲级结构的增强电路,使功率器件在负载瞬态变化时,栅极能够及时响应,从而避免了较大的电压上冲与下冲。加入缓冲级电路以后,系统的稳定性变差,采用密勒补偿和前馈补偿对其进行频率补偿,增加系统的相位裕度,使系统稳定。采用CSMC 0.5 μm工艺,利用Cadence工具完成了整体电路的设计、前仿真、物理版图设计和后仿真,并进行了流片。测试结果表明,设计的LDO输出电压为2.5 V,负载电流在10 mA和300 mA之间变化时,电压最大变化48 mV,响应时间为12.4 μs。     

Low-Dropout Regulators With Adaptive Reference Control and Dynamic Push–Pull Techniques for Enhancing Transient Performance

An adaptive reference control (ARC) technique is proposed for minimizing overshoot/undershoot voltage and settling time of low-dropout regulators. Linear operation provided by the ARC technique can dynamically and smoothly adjust the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In addition, a dynamic push-pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5%, and 70%, respectively, when load current changes between 1 and 100 mA.     

A 3 A sink/source current fast transient response low-dropout Gm driven linear regulator

A 3 A sink/source G_m-driven CMOS low-dropout regulator(LDO),specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m(transconductance)driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm~2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.     

一种快速瞬态响应的无片外电容LDO的设计

基于上华0.5μm工艺,设计了输入电压范围为3.5～6.5V,输出电压为3.3V,最大输出电流为100mA的CMOS无片外电容的低压差线性稳压器.提出了一种自动检测网络用来快速感应负载电流的变化,抑制输出电压的跳变,改善了负载瞬态响应.在稳定性方面,采用miller补偿,加之第二级采用了输出电阻很小的buffer结构[1],这样主极点和次极点分离很远使得系统稳定.仿真表明,该LDO在VIN=6.5V和VIN=3.5V下under-shoot分别为156mV和135mV,overshoot分别为145mV和60mV,线性调整率和负载调整率分别为0.023%和0.5%.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

一种1.2V,80mA,5μF快速瞬态响应、高稳定性LDO的设计

基于上华0.5μm工艺,设计了输入电压为1.5V,输出电压为1.2V,最大输出电流为80mA,用于DC/DC里的CMOS低压差线性稳压器(Low-dropout regulator),作为带隙基准输出端的后续模块,以达到滤波和提高参考电压精度的目的。提出了一种补偿网络,可以保证负载电流发生变化时,相位裕量不发生变化;在补偿网络的基础上添加一个感应电容能够快速跟踪极点的变化,从而保证在负载电流跳变瞬间稳定性保持不变,防止了输出电压发生振荡的情形。此外,设计了一种瞬态响应提高电路结构来改善负载瞬态响应。仿真结果表明,在tt corner下该LDO线性稳压器在负载电流为1mA和80mA时的相位裕度均为83°,环路增益为80dB,流片测试结果显示过冲电压和欠冲电压均不超过100mV。     

增强升压型DC-DC瞬态响应的电路设计

设计了一种增强升压型DC-DC转换器瞬态响应电路,该电路通过检测负载跳变条件下输出电压的变化,调节误差放大器的跨导和补偿电阻,提高升压DC-DC转换器环路带宽,加快系统的瞬态响应。同时将该电路应用于一款输入电压＜至1.4 V,输出电压2.5～6.5 V的同步升压型DC-DC转换器中,其在0.25 μm CMOS 工艺条件下,芯片仿真结果表明,在500 mA~2 A的负载跳变条件下,与传统同步升压DC-DC转换器相比,芯片的响应恢复时间减小了45%,输出电压的下降和过冲值减少了35%。     

具有快速瞬态响应和低静态电流的CMOS低漏失稳压器设计

 设计了一种具有快速瞬态响应能力的低漏失稳压器,利用提出的一种瞬态响应加速(Transient Response Enhancement,TRE)电路,有效地提高了稳压器的瞬态响应速度,而且瞬态响应速度的提高并不增加静态电流.设计的LDO电路采用0.5μm标准CMOS工艺投片验证,芯片面积为0.49mm².该LDO空载下的静态电流仅23μA,最大带载200mA.在1μF输出电容、200mA/100ns负载阶跃变化时的最大瞬态输出电压变化量小于3.5％.     

基于高摆率误差放大器的无片外电容LDO设计

为了解决无片外电容低压差线性稳压器(LDO)的瞬态响应性能较差的问题,采用跨导提高技术设计了一种高摆率的误差放大器.在误差放大器的基础上,通过电容将LDO的输出端耦合至电流镜构建瞬态增强电路,提升LDO的瞬态响应能力,且瞬态增强电路可以引入两个左半平面零点,改善环路的稳定性.同时,误差放大器采用动态偏置结构,进一步减小...     

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and I_Q of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.     

A high voltage LDO with dynamic compensation network

A high voltage, low-dropout regulator (LDO) with dynamic compensation network is implemented in Nuvoton 0.6 μm BCD technology. The proposed HVLDO makes use of high voltage tolerance DMOS transistors to take most of the voltage press in each path, thus satisfying the requirement for wide input range. Besides, the proposed dynamic compensation network can achieve a great stability performance for the HVLDO structure under different load and input supply conditions. In addition, different output voltage is also implemented in this work and the transient response in each situation is also improved. Experimental result verifies that the proposed LDO is stable for a capacitive load of 1 μF and with a load capability of 30 mA. Moreover, the load transient measurements show that the maximum overshoot and undershoot voltage under a relative low supply are smaller than 83 and 103 mV, respectively; while the line transient measurements show that the output variation are within 50 mV among all circumstances. Besides, the measured quiescent current is only 8 μA under a 4 V supply.