一种新的低功耗BIST测试生成器设计

文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值.     

基于低功耗及加权优化的BIST测试生成器设计实现

测试生成器TPG（Tesl Panern Generation）的构造是BIST（Built—In Self-Test）测试策略的重要组成部分。文章结合加权伪随机测试原理及低功耗设计技术，提出了一种基于低功耗及加权优化的BIST测试生成器设计方案。它根据被测电路CUT（Circuit Under Test）各主输入端口权值构造TPG，在对测试序列优化的同时达到降低功耗的目的。仿真结果验证了该方案的可行性。     

一种新型混合模式BIST的低功耗设计

本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的.     

测试延迟自动生成器

在电压调整器的测试中，测试设备提供的负载电流一般要经一定的时间延迟，才能达到规定值。为此，文章给出了一套在ASL-1000测试平台上开发的高精度、低成本的延迟时间自动生成电路，同时给出了其测试原程序。     

利用BIST技术测试并诊断嵌入式存储器

目前,绝大多数集成电路(IC)都设计有嵌入式存储器,IC的复杂化要求对它进行比传统的合格/不合格更深入一步的测试。随着IC几何尺寸日益浓缩,在制作工艺中应实现诊断测试和内置自修复(BISR)等新技术。在片上系统中,嵌入式存储器是最密集的器件,约占总面积的90％;它也是对工艺中的缺陷最敏感的器件,在片上系统内对它进行充分的测试是十分必要的。     

SOC测试中BIST的若干思考

文章简述SOC测试中BIST的优势，结合SOC设计与测试的相关标准，探讨BIST的发展。     

数字电路ATE的下一代测试生成器程序界面

下一代测生成器（ＮＧＴＧ）采用创新的算法和神经网络技术来生成测试数据与诊断数据，本文详细介绍了ＮＧＴＧ与ＡＴＥ的接口方法。     

一种有效的双矢量测试BIST实现方案

文章提出了一种简单有效的双矢量测试BIST。实现方案．其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法，该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测，证明了该方案在计算量和硬件开销方面的优越性。     

一种低功耗BIST测试产生器方案

低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案，该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑，对LFSR的输出和时钟进行调整，从而得到了准单输入跳变的测试向量集，使得待测电路的平均功耗大大降低，给出了以ISCAS'85/89部分基准电路为对象的实验结果，电路的平均测试功耗降幅在54．4％－98．0％之间，证明了该方案的有效性。     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].     

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

并行BIST可测性设计

提出了ＢＩＳＴ的并行结构，分析了其工作原理。实验结果表明，该方法的测试速度比一般ＢＩＳＴ的速度快Ｋ倍（Ｋ为并行度），而硬件花费与一般ＢＩＳＴ结构相当。     

New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters

Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism.     

A New FPGA for DSP Applications Integrating BIST Capabilities

This work proposes a new FPGA architecture, to meet the requirements of signal processing and testing of current system-on-chip designs. The proposed architecture provides the hardware reuse and the reconfigurability advantages of an FPGA, not only for the system functionality, but also for the system testing, while keeping the performance level required by current signal processing applications. This paper presents the new FPGA model, along with preliminary experimental results that clearly show the possible advantages at the system level of merging design and test in a reconfigurable device.