一种低电压CMOS折叠-共源共栅跨导运算放大器的设计

设计了一种全差分折叠-共源共栅跨导运算放大器,并将其应用于80 MHz开关电容带通Δ-Σ A/D转换器中.该跨导运算放大器采用0.35 μm CMOS N阱工艺实现,工作于2.5 V电源电压.模拟结果表明,该电路的动态范围为80 dB、直流增益63.4 dB、单位增益带宽424 MHz;在最大输出摆幅、建立精度为0.1%时,建立时间为7.5 ns,而功耗仅为7.5 mW.     

一款高增益、低功耗、宽带宽全差分运放设计

基于SMIC 0.18μm工艺模型设计了一种低电压1.8 V下的高增益、低功耗、宽输出摆幅、宽带宽的运算放大器电路。采用增益自举技术的折叠共源共栅结构极大地提高了增益,并采用辅助运放电流缩减技术有效地降低了功耗,且具有开关电容共模反馈(SC-CMFB)电路。在Cadence spectre平台上仿真得到运放具有极高的开环直流增益(111.2 d B)和1.8 V的宽输出摆幅,单位增益带宽576 MHz,相位裕度为58.4°,功耗仅为0.792 m W,在1 p F的负载时仿真得到0.1%精度的建立时间为4.597 ns,0.01%精度的建立时间为4.911 ns。     

用于IRFPA ROIC的高性能缓冲器模块的设计

红外焦平面读出电路(IRFPA ROIC)主要用于焦平面阵列与后续信号处理之间的通信.文章提出了一种用于红外焦平面读出电路的缓冲器模块,包括列缓冲器、高性能的输出缓冲器以及相应的偏置电路.缓冲器均采用单位增益放大器结构,通过放大器的优化设计可实现对不同负载的有效驱动且静态功耗较低.该缓冲器模块用于一款640×512面阵、30μm中心距的中波红外焦平面读出电路,采用CSMC 0.5μm DPTM工艺进行流片加工.仿真结果表明,列缓冲器的开环增益为40.00 dB,单位增益带宽为48.17 MHz(10 pF).输出缓冲器可实现轨到轨的输入,开环增益为39.68 dB,单位增益带宽为46.08 MHz,读出速率高达20 MHz,功耗为16.02 mW(25 pF//5.1 kΩ).该模块输入端拉出的测试管脚可在焦平面读出电路的晶圆测试中帮助验证芯片功能.通过调节测试端口,测试结果与仿真结果大体一致,验证了该缓冲器模块的设计可行.     

低电压全差分运算放大器的优化设计

设计了一种适合于带通SigmaDelta调制器的低电压低功耗全差分跨导放大器。在采用增益提高技术和尾电流复制技术的基础上,对电路参数进行优化,使运放获得了较高的性能。采用0.35μmCMOS工艺,模拟结果表明,环路带宽为278MHz,直流增益大于80dB,输入阶跃为4V时,在0.1%的精度下建立时间为9.1ns,动态范围达到83.2dB,电源电压为2V,总的功耗为4.2mW。     

一种高速CMOS全差分运算放大器

设计并讨论了一种高速CMOS全差分运算放大器.设计中采用了折叠共源共栅结构、连续时间共模反馈以及独特的偏置电路,以期达到高速及良好的稳定性.基于TSMC 0.25 μ m CMOS工艺,仿真结果表明,在2.5V的单电源电压下,运算放大器的直流开环增益为71.9dB,单位增益带宽为495MHz(CL=0.5pF),建立时间为24ns,功耗为3.9mW.     

基于优化时间重叠技术的并行流水线A/D转换器

提出了一种基于优化时间重叠技术的10位300 MHz采样率4路并行流水线A/D转换器的设计方法,该方法降低了对运算放大器的要求。通过理论计算和实例设计,证明了此低功耗设计方法的显著效果。设计了一个用于前端的运算放大器,在CSM 0.35μm CMOS工艺、3.3 V电源电压下,该运放的增益为106 dB,单位增益带宽为402 MHz,建立时间为8.8 ns。采用优化时间重叠技术后,可满足4路并行300 MHz采样率的要求,功耗仅为8.57 mW,可大大降低整个并行流水线A/D转换器的功耗。     

0.18μm低压高速高PSRR集成运放芯片设计

基于0.18μm 1.8V CMOS标准工艺,设计了一个低压、高速、高稳定性、高电源抑制比的集成运算放大器芯片.设计中,采用密勒补偿电容,结合调零电阻补偿技术、集成三支路基准电流源高输出阻抗电流分配电路及一种自偏置和预校准偏置电压源,有效地提高了系统的速度和带宽,并具有优良的电源抑制比.利用Cadence Spectre仿真器,对芯片版图进行后端仿真验证.当负载电阻为100KΩ、负载电容为2pF时,芯片功耗4mW,单位增益带宽900MHz,电源抑制比-100dB,开环直流电压增益68dB,相位裕度102°,建立时间4.5ns,压摆率240V/μs,输出摆幅0.116～1.6V.仿真结果表明,该芯片可应用于中频、低频段的模拟电路系统,尤其适用于处理微弱信号的高性能电子系统.     

用于数字电视接收机中PGA的设计

本文采用新型的电流模放大器和可编程的电阻反馈网络设计了一种高线性度的可编程增益放大器(PGA),单级的电压增益范围为0～20dB,增益步长0.5dB,3dB带宽1.7MHzMHz,两个输入谐波(tone)的频率为0.2MHz和0.3MHz,输出摆幅为峰峰值1V时,IM3大于60dB.在3.3V电源电压时功耗为2.38mW.     

一种降低高频噪声的前置全差分运算放大器

提出了一种降低高频噪声的前置全差分放大器.运放内部采用了两组偏置电路,一组用于单位增益缓冲器电路,一组用于放大电路.为了确保电路稳定性又不增加设计难度,将单位增益缓冲器电路与共模反馈回路结合起来.设计采用HHNEC 0.18μm BCD工艺,Cadence Spectre仿真表明,正常工作时共模反馈的环路增益84.93dB,单位增益带宽9.52MHz,相位裕度67.62°;启动时单位增益缓冲器电路的环路增益85.18dB,单位增益带宽8.93MHz,相位裕度67.2°;关断时,单位增益缓冲器电路的环路增益63.26dB,单位增益带宽2.28MHz,相位裕度88.66°.实测表明,设计降低了D类音频功放在开启和关断时的噪声.     

一种全差分增益增强型运算放大器的设计

设计了一种用于高速ADC中的全差分运算放大器。该运算放大器由主运放、4个辅助运放和一种改进型开关电容共模反馈电路组成,主运放采用折叠式共源共栅结构,并引入增益增强技术提高增益。采用SMIC 0.18μm,1.8 V工艺,在Cadence电路设计平台中利用Spectre仿真,结果表明：运放增益达到115 dB,单位增益带宽805 MHz,而功耗仅为10.5 mW,运放在8 ns的时间内可以达到0.01%的建立精度,可用于高速高精度流水线( Pipelined) ADC中。     

低电压高增益带宽CMOS折叠式共源共栅运算放大器设计

本文基于SIMC 0．18μm CMOS工艺模型参数,设计了一种低电压高单位增益带宽CMOS折叠式共源共栅运算放大器。该电路具有相对高的单位增益带宽,并具有开关电容共模反馈电路（CMFB）稳定性好、对运放频率特性影响小的优点,Hspice仿真结果表明,在1．8V电压下,运算放大器的直流开环增益为62．1dB,单位增益带宽达到920MHz。     

一种适用于D类音频功放的全差分运算放大器

介绍了一种应用于超低EMI无滤波D类音频功放的全差分运算放大器结构,可构成积分器,起滤除高次谐波的作用。该运算放大器采用两级结构来获得高增益,第一级为折叠共源共栅,偏置电路采用反馈结构,给整个运算放大器提供偏置电流,从而提高电路的电源抑制比;采用伪AB类输出级提高运放的瞬态响应,稳定运放输出。仿真结果表明,该电路具有良好的性能:增益为113dB,相位裕度为67°;单位增益带宽为1.9MHz,共模抑制比为160dB,电源抑制比为82.7dB;共模反馈环路增益为120dB,相位裕度为62°。     

High-performance NMOS operational amplifier

A high performance operational amplifier 300 mil/SUP 2/ in area has been designed and fabricated in a standard n-channel silicon-gate enhancement/depletion MOS process. Specifications achieved include open-loop gain, 1000; power consumption, 10 mW; common-mode range within 1.5 V of either supply rail; unity-gain bandwidth, 3.0 MHz with 80/spl deg/ phase margin; RMS input noise (2.5 Hz-46 kHz), 25 /spl mu/V; C-message weighted noise -5 dBrnC; and 0.1-percent settling time, 2.5 /spl mu/s.     

High-Speed CMOS Sample-and-Hold Amplifier

The sample-and-hold (S/ H) circuit is a key module for many applications[1 ] totransform a continuous time signal into discrete one. In analog to digital (A/ D)converters,the front-end of the S/ H amplifier must be of both high speed...     

64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器

本文设计了一款二进制增益控制,带有直流失调消除（DCOC）电路以及AB类输出buffer的可编程增益放大器。该放大器采用二极管连接负载的差分放大器结构,电路性能对温度变化及工艺偏差不敏感。根据测试,通过6位数字信号控制,电路可以实现-2dB ~ 61dB的增益动态范围,增益步长1dB,步长误差在 0.38dB以内,最小3dB带宽为92MHz,在低增益模式下,IIP3可达17dBm,1dB压缩点可达5.7dBm。DCOC电路可使该放大器应用于直接变频接收机中,而AB类输出buffer则降低了电路的静态功耗。     

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6-μm process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption     

A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150Ms/s sampling frequency

In order to increase the sampling frequency of SC filters the Precise Opamp Gain (POG) design approach is presented. It is based on the use of large bandwidth opamps with low but precise DC gain. The finite gain value is taken into account in the design phase. This produces capacitor values slightly different from those obtained with the standard design. A BiCMOS opamp with a nominal gain of 96 and unity-gain frequency of 650 MHz is used in a biquadratic lowpass filter with Q=2.8 designed with the POG approach. In a 1.2 μm BiCMOS technology, the prototype lowpass biquad operates with sampling frequency up to 150 Ms/s with 0.2 dB accuracy in the transfer function. For a sampling frequency of 150 Ms/s, the cut off frequency is 15 MHz. The dynamic range (for 1% THD) is 67 dB, and THD is less than -60 dB for a 1.5 Vpp 5 MHz input signal. The chip area is 1 mm², and the power consumption is 20 mW     

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output