A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.     

A new high-density low-voltage SSIMOS EEPROM cell

An efficient low-voltage EEPROM cell is described which occupies an area of 135 µm²when fabricated with 3-µm CMOS technology. To charge and discharge the floating gate, the device relies on Fowler-Nordheim tunneling of electrons between the floating gate and a narrow window of the device channel region. In addition, the control gate is positioned so as to shield the remaining portion of the floating gate from the substrate. The cell can be programmed in 10 ms with a nominal WRITE voltage of 16 V and an ERASE voltage of 12 V. The WRITE/ERASE endurance of the cell is in excess of 10⁶cycles, and the data retention has been shown to be greater than 10 years at 125°C.     

A dual-mode sensing scheme of capacitor-coupled EEPROM cell

A dual-mode sensing (DMS) scheme for a capacitor-coupled EEPROM cell is described. A memory cell structure and a sensing scheme are proposed and estimated. The memory cell combines an EEPROM cell with a DRAM cell. The DMS scheme utilizes the charge-mode sensing of the EEPROM cell. Using this DMS technique, the sensing speed can be enhanced by 36% at a cell current of 15 μA by virtue of the additional charge-mode sensing. Furthermore, the stress applied to the tunnel oxide of the memory transistor can be relieved by decreasing the programming voltage and shortening the programming time. Therefore, with this memory cell structure and sensing scheme, it is possible to realize high-speed sensing in low-voltage operation and high endurance     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

A 1 Mb EEPROM with MONOS memory cell for semiconductor diskapplication

A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm² with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained     

A single poly EEPROM cell structure for use in standard CMOSprocesses

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits     

A mechanism of solar cell degradation in high intensity,high temperature space missions

The behavior of standard space photovoltaic assemblies in a high intensity, high temperature environment (HIHT) is addressed. Experimentally, an HIHT environment, typical for missions to the inner planets of the solar system such as Mercury, characterized by temperatures of 500K and 11 solar constant irradiance in the ultraviolet region below 400 nm, was simulated in a vacuum. Independently of the triple junction cell technology used, module degradation up to 20% in power was observed during several hundred hours of test. Electroluminescence analysis identified discrete top cell shunts close to the cell edge, in particular around the frontside contact pads. Cross‐sectional transmission electron microscopy performed on several degraded cells revealed an etched contact pad metallization/cap layer interface and more importantly, several 100‐nm large, oriented Cu₃P inclusions at the shunted locations. A chemical degradation mechanism is proposed. Short wavelength ultraviolet light interacting with polysiloxanes used as module encapsulant produces hydrogen and methyl radicals. With these building blocks, an organic acid can be formed on external reaction surfaces such as the Ag busbars that simultaneously serve as a source of oxygen. Cu traces present in the Ag segregate to the surface and are transported by this acid to the contact pad of the cell in the liquid phase. An adapted cell design was developed to prevent this degradation mechanism believed to be of relevance for all HIHT space environments. A several hundred micrometer‐wide rim composed of the outermost cell area is electrically separated from the inner cell area and provides a barrier against environmental attack. None of the photovoltaic assemblies featuring this mesa cell design showed any fill factor‐induced power degradation any more. Copyright © 2011 John Wiley & Sons, Ltd.     

Improved EEPROM tunnel- and gate-oxide quality by integration of alow-temperature pre-tunnel-oxide RCA SC-1 clean

The effects of integration of a low-temperature RCA standard clean-1 (SC1) on the tunnel- and gate-oxide charge-to-breakdown (Q_BD) and voltage ramped dielectric breakdown (VRDB) distribution in a 0.7 μm CMOS EEPROM process technology were studied. A low-temperature (<65°C) SC1 used to clean the wafer surface prior to tunnel oxidation resulted in a significantly higher tunnel-oxide Q_BD, as well as improved gate-oxide Q_BD and mode-B failure rates compared to that for a traditional high temperature (>80°C) SC1. The reduced silicon diode etchrate of the low-temperature SC1 allowed for additional gate-oxide annealing during the gate oxidation cycle, while keeping the overall thermal budget (Dt)^1/2 for the technology equivalent to that with the higher temperature SC1. This resulted in improved gate-oxide VRDB distributions and QED values on large capacitor structures. The tunnel-oxide QBD improvement was most likely due to reduced surface roughness in the tunnel-oxide window regions with the lower temperature SC1. The process including the low-temperature SC1 was also proven to provide equivalent yield to the process with the high temperature SC1 on a 0.7 μm, 7 nS 128 macrocell EEPROM programmable logic device     

The impact of three-dimensional effects on EEPROM cell performance

Device simulation is used to investigate three-dimensional effects in small electrically erasable programmable read-only memory (EEPROM) cells. Threshold voltage, tunnel currents, write speed, and the effects of misregistration are characterized for a structurally parameterized generic FLOTOX EEPROM cell. The results indicate considerable sensitivity to three-dimensional effects. Design insights for small EEPROM cells are discussed     

Improving radiation hardness of EEPROM/flash cell by N2Oannealing

The effects of an N₂O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co⁶⁰ irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K. However, by adding an N₂ O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K. N₂O annealing also improves the after-irradiation program and erase efficiencies. The N₂O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

兵力需求的运作机理研究

兵力需求的影响因素有很多,研究这些因素之间的关系及对兵力需求的影响是一个新的课题.提出了兵力需求运作机理的研究框架,在此基础上,依照辨析关键因素、分析因果关系、评价相互影响、分析计算结果的研究步骤,采用因果关系图、层次分析法(AHP)、网络分析法(ANP)等方法,结合实例对具体问题进行了详细分析.通过研究,得出了影响兵力需求的关键因素之间的量化关系,结论具有一定的科学性.     

电子商务平台的演化逻辑和运营机理

数字经济时代的电子商务平台已演化为一种围绕着数据资源和数据技术体系而构建的数据化平台生态系统,极大地降低了交易成本,提高了生产效率,优化了经济结构。首先介绍了电子商务发展的宏观环境和电子商务平台的概念,然后对中国电子商务平台的演化和电子商务平台的运营机理进行了分析。     

The operational mechanism of ferroelectric-driven organic resistive switches

The availability of a reliable memory element is crucial for the fabrication of ‘plastic’ logic circuits. We use numerical simulations to show that the switching mechanism of ferroelectric-driven organic resistive switches is the stray field of the polarized ferroelectric phase. The stray field modulates the charge injection from a metallic electrode into the organic semiconductor, switching the diode from injection limited to space charge limited. The modeling rationalizes the previously observed exponential dependence of the on/off ratio on injection barrier height. We find a lower limit of about 50 nm for the feature size that can be used in a crossbar array, translating into a rewritable memory with an information density of the order of 1 Gb/cm².     

A design of experiment analysis of serial EEPROM endurance

The results of a study using a design of experiments approach to examine the effects of environmental operating conditions on serial EEPROM endurance are presented. The conditions studied in the experiment were operating temperature, applied voltage, device type, array usage, write cycles per day, data pattern, and write pulse width. An ANOVA table showing the significant effects and an estimation of the value of the effects using an error minimization technique is presented. While the techniques presented are relatively simple, they may be useful as a quick check of acceleration effects in EEPROM endurance cycling, without the use of extensive factorial experiments. The results show temperature, array size and voltage to be the most important effects on EEPROM endurance cycling. The temperature effect matches other published data.     

Equivalent cell approach for extraction of the SILC distribution inflash EEPROM cells

A new method for characterizing the distribution of the stress-induced leakage current (SILC) in flash memories is presented. The statistics of the leakage parameters are extracted directly from the time dependence of the threshold voltage distributions obtained in a single gate-stress experiment, without any need for tracking the behavior of the individual cells. The new technique can be used for fast evaluation and reliability projections, as well as providing a tool for statistical investigation on the oxide leakage mechanisms     

Fabrication and characterization of a new EEPROM cell with spacer select transistor

In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 /spl mu/m/sup 2/ with 0.18 /spl mu/m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests.     

Electrical/thermal properties of nonplanar polyoxides and theconsequent effects for EEPROM cell operation

The electrical/thermal properties of nonplanar polyoxides and the resulting effects for EEPROM operational margins are reported. The polyoxide between floating gate (FG) and control gate (CG) of FLOTOX-type EEPROM cells is nonplanar because it always contains edges, where CG wraps over FG. At such edges a highly stable electrical passivation of Fowler-Nordheim (FN) leakage currents occurs, which can cause a degradation of EEPROM operational margins, due to an electron discharge mechanism from the FG of charged EEPROM cells during the first charging operation after conventional baking. The EEPROM cell study includes the dependence on repeated passivation/depassivation of the polyoxide, on baking temperature and baking time. It is found that the average magnitude of the electron discharge is reduced after each passivation/depassivation cycle, which points to a progressive increase of the number of electrons captured in deep neutral electron traps at the polyoxide edges. Analysis of the temperature dependence leads to an activation energy (thermal detrapping energy of the electrons) of 1.3 eV for the degradation mechanism of EEPROM cell operational margins as well as the nonplanar polyoxide depassivation