SiGe HBTs高频特性模拟分析

本文详细分析了下述问题：（１）在基区厚度减薄到几十纳米后,发射区时间常数、集电区时间常数对ＳｉＧｅＨＢＴｓ的高频特性的影响;（２）低掺杂浓度发射区层对发射区渡越时间的影响;（３）在发射结耗尽层中,除了固定电荷因素引起的电容外,发射结正常工作加正向偏压时,由于自由载流子注入引起的ＥＢ结电容．由以上物理分析可以得出器件的有关参数,并由器件的等效电路,对器件的高频特性进行分析和模拟,对影响器件高频特性的参数进行优化．     

InGaAsP／InP掩埋条型激光器的漏电流分析

本文针对Ｐ－Ｎ－Ｐ－Ｎ埋区结构中的漏电流，用广义Ｐ－Ｎ－Ｐ－Ｎ三端器件的理论模型，细致地分析和模拟计算了Ｐ－Ｎ－Ｐ－Ｎ掩埋型ＢＨ激光器的漏电流特性，并据此给出了优化设计器件的数据曲线．通过具体的激光器工艺，我们做出的ＦＢＨ激光器的漏电流大大减小，激光器的线性输出光功率可高达２０ｍＷ，室温寿命超过１０万小时．     

Si／SiGe HBT高频特性的模拟与分析

给出了适用于分析复杂结构ＨＢＴ的电荷传输延迟时间及截止频率的电荷分配模型（ＣＰ）。模拟了Ｓｉ／ＳｉＧｅＨＢＴ的高频特性。模拟结果显示Ｓｉ／ＳｉＧｅＨＢＴ的频率特性较ＳｉＢＪＴ大为改善，而基区及集电结ＳＣＲ区的电荷输运时间将成为提高Ｓｉ／ＳｉＧｅＨＢＴ截止频率的主要制约因素。与实验报道的对比证实了本模型可作为优化器件设计的有效手段。     

InP／InGaAsP异质结双极晶体管发射极条长及基区宽度的选择

本文以Ｅｂｅｒｓ－Ｍｏｌｌ模型为基础，对ＩｎＰ／ＩｎＧａＡｓＰ异质结双极晶体管的高频小信号调制性能进行计算机辅助分析，研究了影响器件高频性能的几个主要模型参数，讨论了在一定的工作电流下，发射极条长及基区宽度对器件高频小信号调制性能的影响，给出了优化选择发射极条长及基区宽度的近似方法。     

应变补偿InGaAsP/InP量子阱DFB激光器与“扇形”光放大器的集成

本文在国内首先报道采用ＭＯＶＰＥ技术研制成功了ＩｎＧａＡｓＰ／ＩｎＰ应变补偿型量子阱ＤＦＢ激光器与“扇形”光放大器的集成器件，实现了３０ｍＷ单纵模工作．采用调制光放大器、静态偏置ＤＦＢ激光器的方法，产生了低啁啾、高功率的单纵模高频光脉冲．集成器件的研制成功，为其它含介质光栅反射器的光子集成器件的研制开辟了一条广阔的道路．     

高密度可编程逻辑器件ATV2500H／L简介

近年来，随着集成电路技术的飞速发展，出现了一种用户可定义其逻辑功能的器件－可编逻辑器件，简称ＰＬＤ器件。其发展经历了ＰＲＯＭ、ＦＰＡＬ、ＰＡＬ、ＧＡＬ，直至现在广泛应用的大规模ＰＬＤ器件ＥＰＬＤ、ＣＰＬＤ及目前最流行的可编程逻辑门阵列ＦＰＧＡ。本文详细介绍了美国受特梅尔公司的ＥＰＬＤ－ＡＴＶ２５００Ｈ／Ｌ的内部结构和功能特点。读者只要再学会ＴＡＮＧＯ－ＰＬＤ、ＡＢＥＬ、ＣＵＰＬ等语言中的一种，便能     

一种高频高压双极性功率器件的研究

针对常规双极功率晶体管（ＢＰＴ）中存在的高频、高电流增益和高ＣＥ击穿电压间的固有矛盾，本文基于Ｋｏｎｄｏ提出的ＧＡＴ结构，利用刻槽淀积Ｐ＋多晶硅基区的新工艺，研制了一种高频高压双极性功率器件，并对该器件的基区电场屏蔽效应进行了解析研究，实验获得了预期的效果。     

一种新型的双极功率器件—BST

针对常规双极功率晶体管（ＢＰＴ）中存在的高频、高电流增益和高ＣＥ击穿电压间的固有矛盾，基于一新工艺提出了一种新型的双极功率器件──ＢＳＴ（ＢａｓｅＳｈｉｅｌｄｉｎｇＴｒａｎｓｉｓｔｏｒ）结构。分析了ＢＳＴ夹断后的两维电场解析解，可知深Ｐ＋多晶硅基区的引入对有源Ｐ基区产生明显的电场屏蔽效应，该基区屏蔽效应随Ｐ＋基区深入Ｎ－区中的深度Ｌ的增加以及相邻Ｐ＋基区间距２Ｄ的减小而增强。正是这种基区屏蔽效应，使得ＢＳＴ的特征频率ｆＴ、电流增益ｈｆｅ和ＣＥ击穿电压ＢＶｃｅ０都较常规ＢＰＴ大为提高，较好地解决了常规ＢＰＴ中存在的主要矛盾。实验验证了理论分析的结果。     

VBR MPEG—2视频编码器的实时实现

文章在分析了ＩＢＭ公司最新的ＭＰＥＧ２视频编码专用芯片ＭＰＥＧＳ４∶２∶０芯片支持ＶＢＲ视频编码的特性,针对这些特性设计了ＶＢＲ视频编码比特率控制算法,同时,阐述了如何利用ＭＰＥＧＳ４∶２∶０,配合可编程逻辑器件和ＤＳＰ芯片,实现ＡＴＭ信道中可变比特率ＭＰＥＧ２视频编码器。     

光控功率开关BMFET的特性分析与数值模拟

讨论了光驱动ＢＭＦＥＴ作为光控功率开关的工作原理，根据理论分析和计算机模拟讨论了器件结构参数和外加偏置电路与工作特性的关系，为器件优化设计提供依据。     

A CMOS image sensor module applied for a digital still camerautilizing the TAB on glass (TOG) bonding method

The world's smallest (105×55×20 mm) and lightest (130 g) digital still camera has been developed, in which a 330 K pixel complementary metal-oxide-semiconductor (CMOS) image sensor chip is used as an image sensor. The authors have developed a new thinner and smaller image sensor module, called tape automated bonding (TAB) on glass (TOG) module, using the anisotropic conductive paste (ACP) interconnection method. The TOG production process was established by obtaining optimum bonding conditions for both optical glass bonding and CMOS chip bonding to the TAB tape. The bonding conditions including sufficient bonding margins, were mainly studied. The TOG module obtained good imaging properties, It also has a high reliability such as thermal cycle test (-40 to +110°C/30 min, 2000 cycles) and the high temperature storage test (60°C, 90% RH, 3000 h). The stable production process was confirmed by fabricating an automatic bonding machine     

微电子封装中芯片焊接技术及其设备的发展

概述了微电子封装中引线键合、载带自动键合、倒装芯片焊料焊凸键合、倒装芯片微型焊凸键合等芯片焊接技术及其设备的发展 ,同时报告了世界著名封装设备制造公司芯片焊接设备的现状及发展趋势。     

大型液晶显示用COF带的现状和未来

概述了从TAB带到COF带的转换,大型LCD用的COF带的微细线路形成技术和高可靠性技术以及COF带制造技术的未来。     

红外探测器倒装互连技术进展

随着红外焦平面技术的发展,红外探测器探测波段已由单波段变为双色及四色波段,半导体元件的封装数量由最初的数十个发展到数百万个,I/O输出密度不断增大,传统微互联技术如引线键合技术、载带自动焊技术等已根本无法满足器件要求。倒装焊技术以其封装尺寸小、互联密度高、生产成本低的特点越来越受到人们的亲睐。倒装互连工艺主要包括:UBM 制备、铟膜沉积、回流成球、倒压焊、填充背底胶。介绍了各工艺步骤的发展状况,并对铟膜沉积、铟柱增高工艺进行详细阐述。     

耐高温丙烯酸酯压敏胶带在柔性电路板中的应用

双面压敏胶带在柔性电路板组装行业有着广泛和大量的应用.综述了柔性电路板行业对压敏胶带的常规性能要求,从被粘材质和胶带种类以及测试要求等方面逐一说明,提供了使用指南.此外,还特别介绍了耐高温丙烯酸酯压敏胶带在柔性电路板行业的应用和性能表现,适合于需要在柔性电路板回流焊工艺前进行表面粘贴的应用,也可用于其他有耐高温性能要求的粘接应用.     

Numerical study on the bonding tool position, tip profile and planarity angle influences on TAB/ILB interconnection reliability

Tape automated bonding (TAB) is a widely used interconnection technology for high-pincount and fine-pitch IC packaging. In this study, a three-dimensional computational model was developed for analyzing TAB inner lead bonding (ILB) process. This experimental study on the thermomechanical properties of copper leads was achieved using high precision micro-force tensile tests. A stress–stain relation between the copper lead and different temperature ranges was successfully implemented into the finite element model to study large plastic deformation in ILB formation. The resulting ILB lead profile and bump sinking values obtained from the simulations agreed well with the experimental observations from actual manufacturing data with the same bonding parameters. The tool position and lead length effects are analyzed to study the residual stress distribution after ILB. A 10-lead model was developed to study how the tool tip profile and planarity ‘angle affect the co-planarity between the bonding tool and the stage. The numerical results show that the permissible tool profile variance should not exceed 1.25 μm and the acceptable planarity angle is 0.005° to achieve the minimum bump deformation requirement.     

Highly reliable flip-chip-on-flex package using multilayered anisotropic conductive film

Anisotropic conductive film (ACF) has been used as interconnect material for flat-panel display module packages, such as liquid crystal displays (LCDs) in the technologies of tape automated bonding (TAB), chip-on-glass (COG), chip-on-film (COF), and chip-on-board (COB). Among them, COF is a relatively new technology after TAB and COG bonding, and its requirement for ACF becomes more stringent because of the need of high adhesion and fine-pitch interconnection. To meet these demands, strong interfacial adhesion between the ACF, substrate, and chip is a major issue. We have developed a multilayered ACF that has functional layers on both sides of a conventional ACF layer to improve the wetting properties of the resin on two-layer flex for better interface adhesion and to control the flow of conductive particles during thermocompression bonding and the resulting reliability of the interconnection using ACF. To investigate the enhancement of electrical properties and reliability of multilayered ACF in COF assemblies, we evaluated the performance in contact resistance and adhesion strength of a multilayered ACF and single-layered ACF under various environmental tests, such as a thermal cycling test (−55°C/+160°C, 1,000 cycles), a high-temperature humidity test (85°C/85% RH, 1,000 h), and a high-temperature storage test (150°C, 1,000 h). The contact resistance of the multilayered ACF joint was in an acceptable range of around a 10% increase of the initial value during the 85°C/85% RH test compared with the single-layered ACF because of the stronger moisture resistance of the multilayered ACF and flex substrate. The multilayered ACF has better adhesion properties compared with the conventional single-layered ACF during the 85°C/85% RH test because of the enhancement of the wetting to the surface of the polymide (PI) flex substrate with an adhesion-promoting nonconductive film (NCF) layer of multilayered ACF. The new ACF of the multilayered structure was successfully demonstrated in a fine-pitch COF module with a two-layer flex substrate.     

耐高温丙烯酸酯压敏胶带在挠性电路板行业的应用

双面压敏胶带在柔性电路板组装行业有着广泛的应用。本文综述了柔板行业对压敏胶带的性能要求,介绍了3M公司新型的耐高温丙烯酸酯压敏胶带,特别适用于要求在柔性电路板回流焊工艺前的表面粘贴应用。     

Applications of magnetic levitation-based micro-automation insemiconductor manufacturing

It is pointed out that the demands for precision and speed in manufacturing processes in the semiconductor industry are not well suited to traditional, large-scale approaches to automation. Consideration of several microautomation approaches has led to the development of a magnetic levitation-based system capable of three-dimensional motions. Such systems are able to move quickly and precisely, and can deliver prescribed forces and moments. Several significant applications of magnetic levitation-based microautomation in semiconductor manufacturing have been identified. These include positioning operations at various scales, such as mask alignment, hybrid circuit assembly, and transport between process stations. Other applications are analytical probing, nondestructive tape automated bonding (TAB) bond testing, and optical system alignment. A prototype system capable of high-speed four-degree-of-freedom motions with 0.5-μm accuracy over small workspaces has been demonstrated     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed