An all-digital phase-locked loop with 50-cycle lock time suitablefor high-performance microprocessors

A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs     

一款应用于无线通信的0.8~4.2 GHz单芯片全数字锁相环频率综合器

本文采用130nmCMOS工艺成功实现了应用于无线通信的0.8 - 4.2 GHz单片全数字锁相环频率合成器。文章提出了一系列的新方法,即采用了高频率分辨率的双带DCO以覆盖系统所需的2.5 GHz至5 GHz带宽;一个溢出计数器可以防止“pulse-swallowing”现象,显著减少了环路锁定时间;提出的NTW-clamp数字模块可以有效防止循环控制字的溢出;修改后的可编程分频器避免了传统架构中失败的边界操作。测量结果表明,该频率合成器的输出频率范围是0.8-4.2 GHz,锁定时间在2.68GHz减少了84%,最好的带内和带外相位噪声性能已达到-100 dBc/Hz,和-125 dBc/Hz,最低参考杂散达到-58dBc。     

A fast-locking PLL with all-digital locked-aid circuit

In this article, a fast-locking phase-locked loop (PLL) with an all-digital locked-aid circuit is proposed and analysed. The proposed topology is based on two tuning loops: frequency and phase detections. A frequency detection loop is used to accelerate frequency locking time, and a phase detection loop is used to adjust fine phase errors between the reference and feedback clocks. The proposed PLL circuit is designed based on the 0.35?µm CMOS process with a 3.3?V supply voltage. Experimental results show that the locking time of the proposed PLL achieves a 87.5% reduction from that of a PLL without the locked-aid circuit.     

基于MCU的锁相环锁定时间测量系统设计

为测量锁相环锁定时间,通过比较各锁相环芯片的接口特点,设计通用的测量系统。该系统包括上位机、下位机软件以及基于AT89C51的控制电路,上位机和下位机使用串口通信。通用性和实时性是系统最大特点,在软件和硬件的设计上保证系统能兼容大多数常用锁相环芯片;并能根据用户输入的控制参数实时控制锁相环且测量其锁定时间。通过实际应用证明,该系统能准确测量锁定时间,有效减少锁相环设计与调试过程中的工作量与复杂度。     

Precise all-digital frequency detector for high frequency signals

A fully digital and simple to implement frequency detector for use with high frequency signals is presented. The new frequency detector can detect small phase movements of much less than one cycle, even though the frequency detector is clocked at a low rate. Existing digital techniques can only detect phase movements of more than one cycle, or require clock rates much higher than the frequency of the signal. The operating limits of the new frequency detector are derived. Examples of the application of the new frequency detector are also given.     

一种先进的N分数锁相环频率合成器

分析了N分数PLL频率合成器，并把 Σ-Δ调制技术应用于频率合成器中，解决了频率分辨率和鉴相器工作频率之间的矛盾，同时大大提高了噪声性能。     

一种具有快速锁定特性的自适应锁相环设计

基于传统电荷泵锁相环(CP-PLL)系统结构设计了一个具有快速锁定特性,环路带宽自适应调节的锁相环。对其中的电荷泵(CP)、低通滤波器(LPF)和环形振荡器(VCO)子模块电路采用了新颖的设计,用UMC 0.18μMix-mode CMOS工艺实现了电路,仿真结果表明系统有较高的性能,适用于USB2.0等高速串行数据传输系统。     

Low power FSK transmitter using all-digital PLL for IEEE 802.15.4g application

This paper presents low power frequency shift keying (FSK) transmitter using all-digital pll (ADPLL) for IEEE 802.15.4g application. In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The resolution of the proposed TDC is improved by using a phase-interpolator, which divides the inverter delay time and the time amplifier, which amplifies the time difference between the reference frequency and the DCO clock. The phase noise of the proposed ADPLL is also improved by using a fine resolution DCO with an active capacitor. To cover the wide tuning range and to operate at a low-power, a two-step coarse tuning scheme with a metal insulator metal capacitor and an active inductor is used. The FSK transmitter is implemented in 0.18 μm 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is 2.2 mm². The power consumption of the ADPLL and transmitter is 12.43 and 22.7 mW when the output power level of the transmitter is ?1.6 dBm at 1.8 V supply voltage, respectively. The frequency resolution of the TDC is 1.25 ps. The effective DCO frequency resolution with the active capacitance and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.83 GHz is ?121.5 dBc/Hz with a 1 MHz offset.     

A PLL clock generator with 5 to 10 MHz of lock range formicroprocessors

A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8-μm CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency     

High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 μA. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 μm CMOS technology to employ the proposed capacitor multiplier.     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.     

An optimal time multiplication free algorithm for edge detection on a mesh

This paper demonstrates an optimal time, fully systolic algorithm for edge detection on a mesh connected processor array. It uses only inexpensive addition and comparison operations which makes it ideal for fine grained parallelism in VLSI. Given anN xN image in the form of a two-dimensional array of pixels, our algorithm computes the Sobel and Laplacian operators for skimming lines in the image and then generates the Hough array using thresholding. The Hough transforms forM different angles of projection are obtained in a fully systolic manner inO(M+N) time, which is asymptotically optimal. In comparison, a previously published multiplication free algorithm has a time complexity ofO(NM). An implementation of our algorithm on a mesh connected finegrained processor array is discussed, which computes at the rate of approximately 170,000 Hough transforms per second using a 50 MHz clock.This research was partially supported by National Science Foundation under Grant No. MIP 8902636     

Efficient frequency multiplication by odd factors without idlers

Antiparallel connection of two varactors in a multiplier as a means of efficient idlerless frequency multiplication by odd factors is discussed. For a tripler, the dependence of efficiency, output and dissipated power on input frequency is shown. A practical multiplier and its properties are described.     

一种可重新配置分辨率的全数字可综合的延迟型LINC发射机基带

The linear amplification with nonlinear component transmitter is a promising solution to high efficiency and high linearity amplification for non-constant envelope signals.An all-digital synthesizable baseband for a delay-based LINC transmitter is implemented.This paper proposes a standard-cell based synthesizable methodology which can be applied in the ASIC process efficiently without performance degradation compared to the manual layout.A scheme to overcome the limited resolution of conventional phase detectors is proposed.It employs alternative phase detector structures to provide reconfigurability for higher resolution after fabricating,resulting in an11 ps resolution improvement.Due to the PVT variation,an adaptive calibration scheme focusing on the inherent imbalance between two delay lines is depicted,which reveals an effective EVM enhancement of 5.37 d B.This baseband chip is implemented in 0.13 m CMOS technology,and the transmitter with the baseband has an EVM of –28.96 d B and an ACPR of –29.51 d B,meeting the design requirement.     

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10²~10³ times higher than conventional PLL synthesizers, and spurs of less than -60 dB     

一种数字调频系统专用频率合成芯片的设计

针对汽车音响收音数字调谐系统的实例,介绍了一种广播用双波段锁相环频率合成芯片的设计方法。设计采用串行端口按位传输数据的方式,在程序分频器部分使用了吞脉冲技术,不仅简化了控制器的操作,同时也获得了较高的频率分辨力,实际产品具有广泛的市场前景。     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain. Michael Chan received his bachelor degrees in Electrical Engineering and Computer Science from the University of Queensland in 2003. He is currently working towards his PhD at the same institution. His research interests include the design of high-speed clock and data recovery systems, and high speed phase locked loops. Adam Postula received the M.S. degree in electrical engineering from the Warsaw University of Technology, Poland, in 1974 and the Ph.D. degree in signal processing from the Poznan University of Technology, Poland, in 1981. He was an Electronic System Designer with ABB Sweden and a Researcher with the Royal Institute of Technology, Stockholm, Sweden, from 1983 to 1992. He led the development of high-level synthesis tools at the Swedish Institute of Microelectronics and was engaged in VHDL standardization in Europe. Since 1995, he has been a Senior Lecturer in the Department of Computer Science and Electrical Engineering, University of Queensland, Brisbane, Australia. His research interests include digital system design methodology, synthesis of digital systems, specialized processor architectures, and VLSI signal processing. Ding Yong received his PhD from University of London in electrical engineering in 1991. He was with National University of Singapore as a research scientist working in industrial research projects on data channel and servo-system for CD technology. In 1995, he joined VLSI design group of Western Digital as a principle engineer, where he was engaged in the IC design of Hard Disk Controller and CD-ROM Decoder and Controller. From 2000, he has been leading a mixed-signal design group as design manager and chief architect with Nano Silicon responsible for development of high-speed serial data transmission IPs. Lech Jóźwiak is an Associate Professor, Head of the Section of Digital Circuits and Formal Methods, at the Faculty of Electrical Engineering, Eindhoven University of Technology, The Netherlands. He received his M.Sc. and Ph.D. degrees in Electronics from the Warsaw University of Technology, Warsaw, Poland, in 1976 and 1982, respectively. From 1979 to 1986, he was a chief of two R&D teams in the Research Institute of Computers in Warsaw, and consultant to the United Nations Industrial Development Organization and industry. From 1986, he works mainly in the Netherlands, but also from time to time in USA, Canada, Australia, Belgium and Poland, combining advanced theoretical research with professional engineering practice and collaborating with industry, academia and governments. He is an author of a new information-driven approach to digital circuit synthesis, and new theories and methodologies of information relationships and measures, general decomposition and quality-driven design that have a considerable practical importance. He is also a creator of a number of practical products in the fields of application-specific (embedded) systems and EDA tools. His research interests include system, circuit, information and design theories and technologies, decision and optimization methodology, artificial intelligence, circuit and system design and EDA, re-configurable and massively parallel high-performance systems, embedded systems, and system dependability, analysis and validation. He is an author of more than 130 journal and conference papers and of some book chapters. He is a Director of EUROMICRO, co-founder and Steering Committee Chair of the EUROMICRO Symposium on Digital System Design, VIP in the IEEE International Symposium on Quality Electronic Design, program committee member of many other conferences, member of IEEE, EDAA, and of the Advisory Committee of the IEE Professional Network Embedded and Real-Time System Engineering. He is an advisor to the industry, Ministry of Economy and Commission of the European Communities in the fields of microelectronics, information technology, technology development and transfer, and SMEs.     

An improved flux observer based on PLL frequency estimator for sensorless vector control of induction motors

This paper presents an improved method of flux estimation for sensorless vector control of induction motors based on a phase locked loop (PLL) programmable low-pass filter (LPF) and a vector rotator. A PLL synchronized with the voltage vector is used for stator frequency estimation. The pure integration of the stator voltage equations is difficult to implement and LPFs with a fixed cutoff provide good estimates only in the relatively high frequency range-at low frequencies, the estimates fail in both magnitude and phase. The method proposed corrects the above problem for a wide range of speeds. Simulations and experimental results on a 0.25-hp three-phase induction machine verify the validity of the approach.