Designing dependable logic controllers using algebraic specifications

Formal methods can strongly contribute to improve dependability of logic controllers during design, by providing means to avoid flaws due to designers’ omissions or specifications misinterpretations. This article presents a formal synthesis method that is aimed at obtaining the control laws of a logic system from specifications given in natural language. The formal framework that underlies the method is a Boolean algebra for logic discrete event systems. The operations and relations of this algebra enable to represent controller specifications formally, to detect inconsistencies within specifications and to generate control laws from a consistent specifications set. The scalability of this method is clearly demonstrated with the help of the case study of an experimental manufacturing line.     

Implementation of a RISC microprocessor for programmable logic controllers

A special purpose RISC (reduced instruction set computer) microprocessor for programmable logic controllers (PLC), named PLCRISC, is proposed. To develop an optimal PLCRISC, we analysed existing PLC programs currently used in factories, with special attention to the instruction execution characteristics and features required for a high performance PLC processor. Based on this analysis, an optimal RISC-style instruction set and an architecture suitable for the required features are suggested. In particular, the instruction format, the instruction pipeline, and the detailed internal architecture are the significant characteristics of the proposed PLCRISC. The performance enhancement achieved with a PLCRISC is seen from a straightforward evaluation. ASIC implementation with VHDL is also discussed. The PLCRISC is under fabrication in a 0.8 μm CMOS technology.     

Formal modeling and synthesis of programmable logic controllers

Programmable logic controllers (PLCs) are complex cyber-physical systems which are widely used in industry. This paper presents a robust approach to design and implement PLC-based embedded systems. Timed automata are used to model the controller and its environment. We validate the design model with resort to model checking techniques. We propose an algorithm to generate PLC code from timed automata and implement this algorithm with a prototype tool. This method can condense the developing process and guarantee the correctness of PLC programs. A case study demonstrates the effectiveness of the method.     

The development of a program generator for programmable logic controllers

Programmable logic controllers (PLC) are very widely used for sequential logic control in manufacturing environments. PLCs serve to integrate materials handling and processes in automated manufacturing systems. Due to changing demands on manufacturing systems, frequently new control software needs to written and changes need to be made to existing control software. The productivity of such software development efforts can benefit from a software generation tool. We present an approach for the development of such a tool.     

NIPAD: a non-invasive power-based anomaly detection scheme for programmable logic controllers

Industrial control systems (ICSs) are widely used in critical infrastructures, making them popular targets for attacks to cause catastrophic physical damage. As one of the most critical components in ICSs, the programmable logic controller (PLC) controls the actuators directly. A PLC executing a malicious program can cause significant property loss or even casualties. The number of attacks targeted at PLCs has increased noticeably over the last few years, exposing the vulnerability of the PLC and the importance of PLC protection. Unfortunately, PLCs cannot be protected by traditional intrusion detection systems or antivirus software. Thus, an effective method for PLC protection is yet to be designed. Motivated by these concerns, we propose a non-invasive powerbased anomaly detection scheme for PLCs. The basic idea is to detect malicious software execution in a PLC through analyzing its power consumption, which is measured by inserting a shunt resistor in series with the CPU in a PLC while it is executing instructions. To analyze the power measurements, we extract a discriminative feature set from the power trace, and then train a long short-term memory (LSTM) neural network with the features of normal samples to predict the next time step of a normal sample. Finally, an abnormal sample is identified through comparing the predicted sample and the actual sample. The advantages of our method are that it requires no software modification on the original system and is able to detect unknown attacks effectively. The method is evaluated on a lab testbed, and for a trojan attack whose difference from the normal program is around 0.63%, the detection accuracy reaches 99.83%.     

A study on the performance impact of programmable logic controllers based on enhanced architecture and organization

Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these devices, the typical role of PLCs in automation systems becomes restricted to a simple controller, since applications with more sophisticated computational requirements tend to be handled by external processing units along with the PLCs. To solve this issue, this work improves novel architecture proposals based on data flow machines, circuit simulation theory, and the memoization technique to achieve a performance boost based on the scan time reduction. Along with the architectural improvements, this paper evaluates the impact of different execution units’ types and quantities in a cycle-accurate simulator (CAS) that was specially developed to simulate the PLC cores. Furthermore, in order to perform a robust and complete evaluation, the silicon areas of the simulated architectures are calculated using the McPAT framework to establish the performance/area relationship of the simulated cores. Evaluation results show best scan time reductions of up to 68% for cores with single execution units and up to 89% for cores with multiple execution units, as well as a best-case of 50% scan time reduction with an acceptable impact on the silicon area. Lastly, the evaluation of the results of the proposed improved cores with multiple execution units shows that they outperform the theoretical performance limit of multiple execution units based on Amdahl’s law up to 4 execution units.     

Freeway traffic control using fuzzy logic controllers

A major cause of freeway congestion before the traffic density becomes critical is the shock wave due to the speed differences between consecutive vehicles. Such disturbance can be reduced if we can impose homogeneous speed control on the vehicles. In this paper, a two-level model-free control scheme using neural-network-based fuzzy logic controllers is proposed which regulates the speed of the freeway through speed advisory boards. Using information from both measurement data and expert knowledge (e.g., environmental information and psychological factors), it is expected that this controller will outperform the conventional ones.     

A novel framework to evaluate programmable logic controllers: a fuzzy MCDM perspective

A programmable logic controller (PLC) is a real-time system operated in severe conditions such as high/low temperatures or tough environments with excessive electrical noise. In particular, a PLC is designed to connect and control multiple mechatronic devices such as facility sensors and actuators and thus the issue of selecting/assessing PLC suppliers is critically important to achieve automatic process control and facility monitoring. In reality, various MCDM (multi-criteria decision making) composed of MADM (multi-attribute) and MODM (multi-objective) based schemes are frequently adopted to tackle the problem of supplier selection. Nevertheless, most of them have the following demerits: (1) the causal dependences between main criteria (or associate attributes) are rarely considered (2) a large number of pairwise comparisons are usually required to conduct the evaluation process. Consequently, a novel framework combining fuzzy DEMATEL, fuzzy AHP, with fuzzy Delphi is proposed to overcome the aforementioned shortcomings. Without requiring tedious pairwise comparisons, the importance weights of main criteria (associated attributes) and the performance scores of PLC vendors are systematically fused into the whole evaluation process. Furthermore, an industrial example is demonstrated to assist PLC practitioners in assessing the top three suppliers, such as SIEMENS (31 %), Allen-Bradley (22 %) and Mitsubishi (13 %).     

Advanced control algorithms embedded in a programmable logic controller

This paper presents an innovative self-tuning nonlinear controller ASPECT (advanced control algorithms for programmable logic controllers). It is intended for the control of highly nonlinear processes whose properties change radically over its range of operation, and includes three advanced control algorithms. It is designed using the concepts of agent-based systems, applied with the aim of automating some of the configuration tasks. The process is represented by a set of low-order local linear models whose parameters are identified using an online learning procedure. This procedure combines model identification with pre- and post-identification steps to provide reliable operation. The controller monitors and evaluates the control performance of the closed-loop system. The controller was implemented on a programmable logic controller (PLC). The performance is illustrated on a field test application for control of pressure on a hydraulic valve.     

面向密码逻辑阵列的可编程控制网络设计与实现

为解决粗粒度密码逻辑阵列控制开销大、控制效率低的问题,在研究主流阵列处理架构下三层控制模型的基础上,提出了一种阵列的四层控制模型,并设计了对应的可编程控制网络。在规模为4×4的可编程控制网络上实现了对AES、A5-1等对称算法的控制流映射。在65 nm CMOS工艺下,DC综合结果显示总面积为13 712μm~2,折合等效与非门数0.95万,占阵列面积0.37%。映射AES和A5-1控制流最高频率分别为1 389 MHz和1 190 MHz,达到面积小、速度快的应用需求。将四层控制模型与三层控制模型进行六个不同性能对比,前者整体性能远超后者,且能满足任意网络互连结构阵列的高效控制需求。     

Multiple-valued logic and optimization of programmable logic arrays

Shows a method of designing programmable logic arrays (PLAs) using multiple-valued input, two-valued output functions (MVITVOFs). A MVITVOF is an extension of the two-valued logic function. An expression for a MVITVOF directly represents a multiple-output PLA with decoders. Each product of the expression corresponds to each column of the PLA, so the number of products; in the expression equals the number of columns of the PLA. The array size of the PLA is proportional to the number of products; the PLA can thus be minimized by minimizing the expression     

专为可编程逻辑设计师提供的节能方案

随着政府实行更为严格的功耗规定,如何进一步降低待机功耗成为工程师设计过程中需要考虑的一个重要因素。现代可编程逻辑器件动态电流要求极低,并能在集成了一个低成本晶振后实现门控时钟网络,对降低电子产品的系统功耗有很大的使用价值。     

Shortening the design cycle for programmable logic

X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis     

Simulation of programmable logic controller

The development and test of a PLC control program takes time, increases equipment down-time, and might damage hardware due to program errors. All of these problems can be eliminated if there is a computer simulation system for testing control programs off line. This paper presented a new method, called Direct Sequential Method, for simulating PLCs. This method resolves a ladder logic sequentially by applying a series of logic deductions. This simulation system has been implemented in C and tested successfully.     

Robustness of temporal logic specifications for continuous-time signals

In this paper, we consider the robust interpretation of Metric Temporal Logic (MTL) formulas over signals that take values in metric spaces. For such signals, which are generated by systems whose states are equipped with non-trivial metrics, for example continuous or hybrid, robustness is not only natural, but also a critical measure of system performance. Thus, we propose multi-valued semantics for MTL formulas, which capture not only the usual Boolean satisfiability of the formula, but also topological information regarding the distance, ε$\epsilon$, from unsatisfiability. We prove that any other signal that remains ε$\epsilon$-close to the initial one also satisfies the same MTL specification under the usual Boolean semantics. Finally, our framework is applied to the problem of testing formulas of two fragments of MTL, namely Metric Interval Temporal Logic (MITL) and closed Metric Temporal Logic (clMTL), over continuous-time signals using only discrete-time analysis. The motivating idea behind our approach is that if the continuous-time signal fulfills certain conditions and the discrete-time signal robustly satisfies the temporal logic specification, then the corresponding continuous-time signal should also satisfy the same temporal logic specification.     

Built-in test for folded programmable logic arrays

Implementing a function using a programmable logic array (PLA) can often be very expensive in terms of area. Folding rows and/or columns of a PLA usually leads to a reduction in area. In this paper the problem of fault detection in folded PLAs is considered. A new fault, the ‘cutpoint’ fault, is described and universal test sets for the detection of this fault are presented. Modifications to existing built-in universally testable design techniques for nonfolded PLAs are presented; the new designs are now applicable to folded PLAs.