A W-Band Medium Power Amplifier in 90 nm CMOS

A W-band CMOS medium power amplifier (PA) is presented in this letter. The circuit is implemented in 90 nm mixed signal/radio frequency CMOS process. By utilizing balanced architecture, the PA demonstrated a measured maximum small signal gain of 17 dB with 3 dB bandwidth from 91 to 108 GHz. The saturation output power $(P_{rm sat})$ is 12 dBm between 90 and 100 GHz for $V_{rm ds}$ of each transistor at 1.5 V. To our knowledge, this is the highest frequency CMOS PA to date.      

A Low-Voltage Broadband Feedforward-Linearized BJT Mixer

A low-voltage, feedforward-linearized bipolar mixer realizes an input$hboxIP_3$of$+$14.3 dBm and an input$hboxIP_2$of$+$54.5 dBm at 2.4 GHz. Conversion (power) gain over the 1–6GHz RF input range is 12.4$,pm,$0.35 dB, while the input$hboxIP_3$is 13.6$,pm,$1.8dBm over the same frequency range. The broadband mixer's RF input impedance varies from 60.3-j7.1 at 2.4 GHz to 57.4-j16.6$~Omega$at 5.8GHz. Measured SSB (50$Omega$) noise figure is 18.6 dB at 2.4 GHz. No on-chip inductors are used in the design, and the 0.14$hbox mm^2$(active area) mixer dissipates 7.2 mW from a (minimum) 1.2 V supply.     

A Compact High-Efficiency CMOS Power Amplifier With Built-in Linearizer

In this letter, a compact high-efficiency CMOS power amplifier (PA) with built-in linearizer that works at 2.4 GHz using TSMC 0.18 $mu$m technology for digital wireless communications applications is presented. The cascode configuration is utilized to overcome the low break-down voltage problem and the hot-carrier effects for high power operations of CMOS devices. The linearizer design reduces the AM-AM quantities to extend the $P_{1 {rm dB}}$ point while the AM-PM distortions are improved as well. The final designed PA exhibits $P_{1 {rm dB}}$ of 20.6 dBm and 24.6% power-added-efficiency (PAE) with 35 dBm output-intercept-point in the third order (OIP3). The saturated output power is 22 dBm with 30% in PAE, while the chip size is less than 1 mm$^{2}$.      

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

A 4–17 GHz Darlington Cascode Broadband Medium Power Amplifier in 0.18-$mu$ m CMOS Technology

This letter presents a broadband medium power amplifier in 0.18- $mu$m CMOS technology. The Darlington cascode topology is used to achieve wide bandwidth, flat gain and power frequency response. For wideband matching consideration, an interstage inductor and series peaking RL circuit are adopted. An output high pass matching circuit is used to maintain gain and power flatness at high frequency. The measured results show that the proposed PA demonstrates a gain of 10 dB from 4 to 17 GHz with less than 2-dB ripple, and a saturation output power of 16 to 18 dBm with PAE of better than 10% and power consumption of 306 mW. The chip size is only 0.67 mm$^{2}$ .      

A Novel 3–5 GHz Active Matched Filter for Impulse Radio Ultra-Wideband

In this letter, a novel active matched filter for UWB-IR lower band (3.1–4.85 GHz) is presented. The signal to noise ratio is improved at the output using a tapped delay line with a common source amplifier. An artificial transmission line is used for wideband impedance matching. The matched filter achieves a power gain of 9.8 dB at center frequency. Input matching is better than ${-}19$ dB and output matching is better than ${-}15$ dB. The averaged SNR improvement is 4.6 dB using peak detection. Input referred 1-dB compression point is 0.7 dBm at the center frequency. The matched filter is biased from a 1.5 V supply with a total power consumption of 38 mW.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

A High Gain 77 GHz Power Amplifier Operating at 0.7 V Based on 90 nm CMOS Technology

A 77 GHz 90 nm CMOS power amplifier (PA) demonstrates a gain of 17.4 dB and a saturated output power of 5.8 dBm at a low supply voltage of 0.7 V. To take care of hot-carrier injection degradation, the supply voltage is reduced from a standard voltage of 1.0 V. The saturated output power is increased to 9.4 dBm with a linear gain of 20.6 dB at 1.0 V operation. The amplifier consists of three-stage common-source nMOSFETs with gate widths of 40, 80, and 160 $mu{rm m}$. To our best knowledge, the developed PA shows the highest gain ever achieved for W-band CMOS amplifier. The measured temperature characteristics suggest that a simple compensation technique is possible by gate bias control.      

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18 $mu$ m CMOS Technology

A 10–40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 $mu$ m CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1$,times,$ 0.67 mm$^{2}$ . The measured results demonstrate a conversion loss of 15.6–17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51–59 dB over 10–40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.      

A 30 GHz Variable Gain Amplifier With High Output Voltage Swing for Ultra-Wideband Radar

This paper reports on the analysis, design and characterization of a 30 GHz fully differential variable gain amplifier for ultra-wideband radar systems. The circuit consists of a variable gain differential stage, which is fed by two cascaded emitter followers. Capacitive degeneration and inductive peaking are used to enhance bandwidth. The maximum differential gain is 11.5 dB with ${pm}1.5$ dB gain flatness in the desired frequency range. The amplifier gain can be regulated from 0 dB up to 11.5 dB. The circuit exhibits an output 1 dB compression point of 12 dBm. The measured differential output voltage swing is 1.23 V$_{pp}$ . The 0.75 mm$^2$ broadband amplifier consumes 560 mW at a supply voltage of ${pm}3.3$ V. It is manufactured in a low-cost 0.25 $mu$ m SiGe BiCMOS technology with a cut-off frequency of 75 GHz. The experimental results agree very well with the simulated response. A figure of merit has been proposed for comparing the amplifier performance to previously reported works.      

A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

A 1.83 GHz 28.5 dBm CMOS Power Up-Mixer

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 $mu{rm m}$ CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is $-$43 dBc.      

A Novel Planar Three-Way Power Divider

A novel planar three-way power divider is proposed. Based on the conventional planar microstrip coupled line technology, the proposed three-way power divider can modify a three-way Wilkinson power divider from a three-dimensional configuration into a two-dimensional one, meanwhile, to keep the length of the circuit to be$lambda/$4. The planar structure enables easy circuit design in printed circuit boards and monolithic microwave integrated circuits. The design concept and implementation are discussed. From the measured results, less than 4.8$pm $0.1dB of the three equivalent insertion losses, less than 19.5dB of the return loss, and better than 17.5dB of isolation at 2.4GHz can be achieved.     

Design and Analysis of a 55–71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process

A 55–71-GHz fully integrated power amplifier (PA) using a distributed active transformer (DAT) is implemented in 90-nm RF/MS CMOS technology. The DAT combiner, featuring efficient power combination and direct impedance transformation, is suitable for millimeter-wave (MMW) PA design. Systematic design procedures including an impedance allocation plan, a compensation line, and a gain boosting technique are presented for the MMW DAT PA. The monolithic microwave integrated circuit (MMIC) performs a high and flat small-signal gain of ${hbox{26}} pm {hbox{1.5}}~{hbox{dB}}$ from 55 to 71 GHz, which covers a full band for 60-GHz wireless personal area network applications. Using cascode devices and a DAT four-way power combination, the CMOS PA delivers 14.5- and 18-dBm saturated output power with 10.2% and 12.2% power-added efficiency under 1.8- and 3-V supply voltage, respectively, at 60 GHz. The maximum linear output power ( $ P _{1~{rm dB}} $) is 14.5 dBm. To the best of our knowledge, the MMIC is the first demonstration of a $V$-band CMOS PA using a DAT combining scheme with highest linear output power among the reported 60-GHz CMOS PAs to date.      

Reduction of Crosstalk Between Dual Power Amplifiers Using Laser Treatment

A cost-effective isolation technique using laser treatment is proposed to suppress the undesired crosstalk between dual power amplifiers (PAs), which are essential to multiple-input multiple-output communications system. Laser treatment not only reduces the small-signal coupling between dual PAs but also enhances the linearity of the PA under dual-PA operation mode. The figure of merit for the small-signal coupling has an improvement of 4.55 dB at 2.45 GHz, and the output power at 3% (${-}$ 30 dB) error vector magnitude (EVM) has a linearity improvement of 6.1 dB under 0-dB interference.      

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-$mu$ m 2.5-V standard I/O FETs in a 0.13- $mu$m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.      

A 16–44 GHz Compact Doubly Balanced Monolithic Ring Mixer

A novel and compact 16–44 GHz ultra-broadband doubly balanced monolithic ring mixer for Ku- to Ka-band applications implemented with a 0.15-$mu$m pHEMT process is presented. The proposed mixer is composed of a C-band miniature spiral balun and a 180$^{circ}$ hybrid formed with an interdigital coupler, a low-pass $pi$-network, and a high-pass T-network. The 180$^{circ}$ hybrid eliminates the use of a cross-over structure for application in the balanced mixer, as well as provides an output port for the RF extraction of up-converter application. This proposed configuration leads to a die size of less than 0.8$,times,$ 0.8 mm$^{2}$ . From the measured results, the mixer exhibits an 11–14 dB conversion loss, a 27–50 dB high LO-to-IF isolation over 16–44 GHz RF/LO bandwidth, and a 1-dB compression power of 14 dBm for both down- and up-converter applications.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

94 GHz Voltage Controlled Oscillator With 5.8% Tuning Range in Bulk CMOS

A 94 GHz fundamental mode voltage controlled oscillator (VCO) is demonstrated using low leakage transistors in a 65 nm digital CMOS process with six metal layers. It achieves a tuning range of 5.8% and phase noise of ${-}$ 106 dBc/Hz at 10 MHz offset from a 94.9 GHz carrier. The output power varies between ${-}$ 4 and ${-}$ 8 dBm over the tuning range. The VCO draws 6 mA bias current from a 1.5 V supply and 6 mA from a 0.8 V supply.