双电测组合法测试半导体电阻率的研究

对双电测组合四探针法测试方块电阻 (Rs)和体电阻率 ( ρ)进行了研究 ,从理论和实践上揭示三种组合模式的共同优点 :测量结果与探针间距无关 ,可使用不等距探针头 ;具有自动修正边界影响的功能 ,不必寻找修正因子 ;不移动探针头即可得知均匀性 .推导出用于体电阻率时的厚度函数 .论述了Rs、ρ、大小样片及边界附近的测试原理 ,给出了Rs 和 ρ的计算公式.     

双电测组合法测试半导体电阻率的研究

对双电测组合四探针法测试方块电阻(Rs)和体电阻率(ρ)进行了研究,从理论和实践上揭示三种组合模式的共同优点:测量结果与探针间距无关,可使用不等距探针头;具有自动修正边界影响的功能,不必寻找修正因子;不移动探针头即可得知均匀性.推导出用于体电阻率时的厚度函数.论述了Rs、ρ、大小样片及边界附近的测试原理,给出了Rs和ρ的计算公式.     

P型外延电阻率表面态的研究

P型硅外延材料是制备微波功率器件的关键基础材料,其电阻率的一致性直接影响器件的性能和可靠性。研究通过对Si、N、B 3种元素进行电负性对比,结合P型外延片电容-电压法(CV法)测试波动和纵向载流子分布(SRP)比较分析,确定了造成P型外延电阻率波动的主要原因,并通过对表面态的控制找到解决方案。     

6英寸高均匀性P型硅外延片的工艺研究

主要进行了6英寸(152.4 mm)高均匀性P型硅外延片的生产工艺研究。利用PE-2061S型桶式外延炉,在重掺硼的硅衬底上化学气相沉积P/P+型硅外延层。通过流场调节工艺、基座包硅工艺、变流量解吸工艺、两步生长工艺等关键工艺的改进,对非主动掺杂效应进行了有效抑制,利用FTIR(傅里叶变换红外线光谱分析)、C-V(电容-电压测试)、SRP(扩展电阻技术)等测试方法对外延层的电学参数以及过渡区形貌进行了测试,得到结晶质量良好、厚度不均匀性<1%、电阻率不均匀性<1.5%的6英寸P型高均匀性硅外延片,各项参数均可以达到器件的使用要求。     

对n型Si外延片表面处理方法的研究

Si外延片是制造半导体器件和集成电路最常用的半导体材料。外延层电阻率是外延片最重要的参数之一,它直接影响器件的性能。简要分析了自动汞探针C-V测试仪测量电阻率前进行表面处理的原因,研究了不同的表面处理方法对电阻率测试结果的影响,发现对于外延层的电阻率ρ>1Ω.cm的n型Si外延片,采用紫外光(UV)表面处理是一种合适的表面处理方法,该方法应用于实际生产测试过程。     

具有三层复合结构的P型硅外延片制备工艺研究

对10.16 cm(4英寸)三层复合结构P型硅外延片的制备工艺进行了研究。利用PE-2061S型桶式外延炉,在重掺硼的硅衬底上采用化学气相沉积的方法成功制备P~-/P~+/P/P~+型硅外延层。通过FT-IR(傅里叶变换红外线光谱分析)、C-V(电容-电压测试)、SRP(扩展电阻技术)等测试方法对各层外延的电学参数以及过渡区形貌进行了测试,最终得到结晶质量良好、厚度不均匀性<3%、电阻率不均匀性<3%、各界面过渡区形貌陡峭的P型硅外延片,可以满足器件使用的要求。     

MgO缓冲层对Si衬底上制备Fe3Si薄膜性能的影响

采用磁控溅射方法和热加工工艺在n型Si衬底上溅射不同厚度的MgO层并制备Fe-Si薄膜层,退火后形成Fe3Si/MgO/Si多层膜结构.利用MgO缓冲层对退火时Si衬底扩散原子进行屏蔽,并分析MgO层对Fe3Si薄膜结构和电学性质的影响.通过X射线衍射仪(XRD)、扫描电子显微镜(SEM)和四探针测试仪对Fe3Si薄膜的晶体结构、表面形貌、断面形貌和电阻率进行表征与分析.研究结果表明:当MgO层厚度为20 nm时生成Fe0.9Si0.1薄膜,当厚度为50,100,150和200 nm时都生成了Fe3Si薄膜,生成的Fe3Si和Fe0.9Si0.1薄膜以(110)和(211)取向为主.随MgO缓冲层厚度增加,Si衬底扩散原子对Fe3Si薄膜的影响减小,Fe3 Si薄膜的晶格常数逐渐减小,晶粒大小趋向均匀,平均电阻率呈现先增大后减小趋势.研究结果为后续基于Fe3 Si薄膜的器件设计与制备提供了参考.     

基于EIT技术的微区薄层电阻测试系统研究

分析了各种半导体材料电阻率测量方法的优缺点及适用性,利用电阻抗成像技术(EIT),探究了一种用来检测Si片内微区薄层电阻率均匀性的无接触测试技术.实现这种测试技术的硬件电路系统主要由激励模块恒流源、驱动模块多路模拟开关、信号处理模块前置放大电路、A/D转换器件和DSP(数字信号处理器)芯片、计算机等构成.分别介绍了各模块的构成与功能,并略述了用一种图像重建算法等位线反投影法进行阻抗分布图像的重建.     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即MFIS(Metal/Ferroelectr c/Irsulator/Semiconductor)电容的方法,并对其进行了SEM、C-V特性测试及ZrO2介质层介电常数分析.研究了C-V存储窗口(Memory WindoW)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7 10左右,在外加电压5V-+5V时存储窗口可达2.52V左右.     

快速恢复外延二极管用150mm高均匀性硅外延材料的制备

利用PE3061D型平板式外延炉,在150mm的重掺As的硅单晶衬底上采用化学气相沉积(CVD)方法制备参数可控且高均匀性的外延层,通过聚光灯、原子力显微镜(AFM)、傅里叶变换红外光谱仪(FT-IR)、汞探针电容-电压测试仪(Hg CV)等测试设备分别研究了外延层的表面形貌、微粗糙度、厚度、电阻率以及均匀性参数。采用了基座浅层包硅技术、周期性滞留层杂质稀释技术、高温快速二次本征生长技术、温场流场调控技术等新型工艺技术,使外延层厚度满足(15±2%)μm,电阻率满足(15±2%)Ω·cm的设计要求,片内厚度和电阻率不均匀性达到<2%的水平。制备的硅外延材料应用于FRED的试产,击穿电压高于125V,晶圆的成品率达到90%以上,满足了120VFRED器件使用要求,实现了自主可控。     

半绝缘SiC单晶电阻率均匀性研究

采用非接触电阻率面分布(COREMA)方法对本实验室生长得到的2英寸(50 mm)4H和6H晶型半绝缘SiC单晶片进行电阻率测试,结果发现数据的离散性大,低者低于测试系统下限105Ω.cm,高者高于其上限1012Ω.cm,甚至在同一晶片内会出现小于105Ω.cm,105~1012Ω.cm和大于1012Ω.cm的不同区域,而有的晶片则电阻率的均匀性较好。将SiC电阻率测试结果与二次离子质谱(SIMS)对晶体内主要杂质V,B和N含量测试结果相结合,初步探讨得到引起掺钒SiC单晶电阻率的高低及均匀性的变化由补偿方式决定,在深受主补偿浅施主模式下,V的浓度控制在2×1016~3×1017cm-3,N的浓度控制在1×1016cm-3左右,深受主钒充分补偿浅施主氮,制备得到的SiC单晶具有半绝缘性,且电阻率均匀性好。     

High resistivity measurement of SiC wafers using different techniques

To establish fast, nondestructive, and inexpensive methods for resistivity measurements of SiC wafers, different resistivity-measurement techniques were tested for characterization of semi-insulating SiC wafers, namely, the four-point probe method with removable graphite contacts, the van der Pauw method with annealed metal and diffused contacts, the current-voltage (I-V) technique, and the contactless resistivity-measurement method. Comparison of different techniques is presented. The resistivity values of the semi-insulating SiC wafer measured using different techniques agree fairly well. As a result, application of removable graphite contacts is proposed for fast and nondestructive resistivity measurement of SiC wafers using the four-point probe method. High-temperature van der Pauw and room-temperature Hall characterization for the tested semi-insulating SiC wafer was also obtained and reported in this work.     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

用于光纤通信的硅光电探测器的研制

根据光纤入户（FTTH）的应用特点,选用外延层厚度和电阻率各不相同的三种硅外延片,研制了用于FTTH的PIN硅光电探测器,并与硅单晶材料的PN结光电二极管进行了全程比对.测量结果表明,PIN探测器的暗电流可达10-11A量级,响应时间为2 ns.分析了Ⅰ层厚度和电阻率对探测器件暗电流、结电容和响应时间的影响及引起特性差别的原因,为设计能满足光纤通信要求的光电探测器提供了依据.     

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

无测试图形薄层电阻测试仪及探针定位

研制出检测U L SI芯片的薄层电阻测试仪,可用于测试无图形样片电阻率的均匀性,用斜置的方形四探针法,经显微镜、摄像头及通信口接入计算机,从计算机显示器观察,用程序及伺服电机控制平台和探针移动,使探针处于规定的位置,实现自动调整、测试;对测试系统中的探针游移造成的定位误差进行分析,推导出探针游移产生误差的计算公式,绘制了理论及实测误差分布图;测出无图形10 0 m m样品电阻率,并绘制成等值线Mapping图.     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

In-line monitoring of 300 mm silicon epitaxial and CZ wafers using surface charge profiler

The surface charge profiler (SCP) offering non-contact electrical characterization of the near-surface region of silicon wafers is discussed. The system permits fully automatic handling of 300- and 200-mm wafers. The SCP method, based on a low intensity illumination a.c. surface photo-voltage principle, does not require any surface preparation. It allows for a fast (600 points/min), high-resolution mapping of the active doping concentration in the near-surface region as well as surface recombination lifetime. The capabilities of the SCP method for process monitoring and development are illustrated with 200- and 300-mm wafers, focusing on the effects of epi growth conditions on the layer uniformity and its resistivity.