基于噪声消除技术的超宽带低噪声放大器设计

基于TSMC 0.18μm工艺研究3 GHz~5 GHz CMOS超宽带无线通信系统接收信号前端的低噪声放大器设计。采用单端转差分电路实现对低噪声放大器噪声消除的目的,利用串联电感作为负载提供宽带匹配。仿真结果表明,所设计的电路正向电压增益S21为17.8 dB~19.6 dB,输入、输出端口反射系数均小于-11 dB,噪声系数NF为2.02 dB~2.4 dB。在1.8 V供电电压下电路功耗为12.5 mW。     

采用新型电流舵结构的增益可调UWBLNA

基于TSMC 0.18μm CMOS工艺,设计了一款工作在3 GHz⁵ GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz5 GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz⁵ GHz工作频段内,LNA获得了25 dB的增益可调范围,最高增益达到24 dB,输入端口反射系数小于-11 dB,输出端口反射系数小于-14 dB,最小噪声系数为2.3 dB,三阶交调点(IIP3)为4 dBm,在1.2 V电压下,电路功耗仅为8.8 mW。     

高增益低功耗CMOS低噪声放大器的设计

本文基于TSMC 0.35μm CMOS工艺,设计了一种工作于2.4 GHz频率下的、高增益、低功耗的低噪声放大器.并在ADS的平台下进行了参数的优化与仿真.其仿真结果表明,该低噪声放大器的最大增益约为16 dB,并且波动范围小于0.3dB;噪声系数约为0.8 dB,IIP3为 1.6 dBm:在1.5 V电源电压供电条件下,电路直流功耗为8 mW.因此,该电路实现了高增益、低功耗的功能.满足实际应用的要求.     

基于噪声消除技术的超宽带CMOS低噪声放大器设计

为满足3.5 GHz单载波超宽带无线接收机的射频需求,设计了一种工作在3～4 GHz的超宽带低噪声放大器。电路采用差分输入的CMOS共栅级结构,利用MOS管跨导实现宽带输入匹配,利用电容交叉耦合结构和噪声消除技术降低噪声系数,同时提高电压增益。分析了该电路的设计原理和噪声系数,并在基于SMIC 0.18μm CMOS射频工艺进行了设计仿真。仿真结果表明:在3～4GHz频段内,S11和S22均小于-10 dB,S21大于14dB,带内起伏小于0.5dB,噪声系数小于3dB;1.8V电源电压下,静态功耗7.8mW。满足超宽带无线接收机技术指标。     

3GHz～5GHz超宽带噪声系数稳定的低噪声放大器

采用共源共栅级结构和源极负反馈电路设计了一款应用于超宽带系统的低噪声放大器电路。结合巴特沃斯滤波器的特性,实现放大器的输入、输出匹配网络,并详细分析了电路的噪声系数。基于TSMC 0.18μm CMOS工艺,在3 GHz～5 GHz频带范围内对电路进行ADS软件仿真。仿真结果表明,在1.8 V供电电压下,功耗为13.2 mW,最大增益达到15 dB且增益平坦,最大噪声系数仅为1.647 dB,输入反射系数S11<-10 dB,输出反射系数S22<-14 dB。     

基于功耗限制的CMOS低噪声放大器最优化设计

分析了进行功耗限制条件下怎样得到低噪声放大器的最优噪声,并就阻抗匹配及小信号电压增益进行了详细讨论。介绍了采用0.25μmCMOS工艺设计的工作在2.4GHz频率下的全集成低噪声放大器。模拟结果表明,在2.4GHz工作频率下,低噪声放大器的功耗为16mW,正向增益S21可达15dB,反射参数S11、S22分别小于-23dB和-20dB,噪声系数NF为2.7dB,三阶互调点ⅡP3为-0.5dB。     

ADI公司推出超低噪声超低失真的高速运算放大器

美国模拟器件公司推出一种新的高速运算放大器——AD8099,它能够将放大器设计中两个基本的误差源(电压噪声和谐波失真)都降至最低。AD8099采用一种先进电路结构专利技术,使其满足传统运算放大器差分输入级基本性能的同时又不牺牲其固有性能。这使得AD8099既能提供极低的电压噪声(0.95nV/(Hz)~(1/2))又能提供极低的失真(-90dB,在10MHz基频条件下),这种新器件在增益为10条件下具有1600V/μs转换速率和5GHz增益带宽乘积。当增益降为2时,其转换速率为600V/μs。     

DC到2.6GHz硅基MMIC放大器

本文采用基于硅基的：BiCMOS工艺设计制作了一款带宽为DC到2．6GHZ的低噪声、高增益MMIC放大器。该放大器为了实现从DC到2．6GHz的带宽，保证有足够的增益和理想的增益平坦度，采用了负反馈结构，两级级联，并选用了一种结构新颖的微波晶体管。该放大器具有功率增益高、频带较宽、噪声系数较小的特点。在仿真过程中其3dB带宽约3GHz，增益为26．6dB(1．5GHz时)，1dB压缩点输出功率约为1dBm；样品的实测结果为3dB带宽约2．6GHz，增益为26dB(1．5GHz时)，1dB压缩点输出功率约为1dBm。     

一种新型超宽带CMOS低噪声放大器设计

结合电阻并联反馈，利用PCSNIM流程设计了一个用于超宽带（UWB）系统的宽带LNA电路。电阻并联反馈降低了输入电路的Q值，使窄带LNA带宽增加，而对NF的影响很小。用TSMC0.18CMOS工艺进行仿真，结果表明，LNA在3．1-5．1GHz带宽范围内NF小于2．9dB。输入匹配优于-10．5dB，功率增益为12．9dB，带内波动仅为1dB。在1．8V电源电压下，核心电路功耗为7．5mW。     

一种用于人体传感器网络的接收器模拟前端

设计了一种用于人体传感器网络的低功耗接收器模拟前端,电路物理层信道利用人体进行通信,并采用了一种宽带信号传输技术,可以在0.8 V电压供电,100 mV输入敏感度条件下传输20 Mb/s的数据。片上的电压偏置电路提供了50Ω的输入阻抗。放大器采用了一种低压低功耗的Cascode结构,具有58 dB的增益,25 MHz的增益带宽积。另外采用了一种结构简单,功耗极低的电流反馈型Schmitt触发器。电路采用SMIC0.13μm标准CMOS工艺设计,面积0.02 mm2,供电电压0.8 V,功耗仅为2.2 mW。     

一种0.8GHz～6GHz CMOS超宽带低噪声放大器设计

给出了一个针对0.8GHz～6GHz 的超宽带低噪声放大器 UWB LNA(ultra-wideband low noiseamplifier)设计。设计采用0.18μm RF CMOS 工艺完成。在0.8GHz～6GHz 的频段内,放大器增益 S21达到了17.6dB～13.6dB。输入、输出均实现良好的阻抗匹配,S11、S22均低于-10dB。噪声系数(NF)为2.7dB～4.6dB。在1.8V 工作电压下放大器的直流功耗约为12mW。     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...     

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low‐noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two‐stage low‐noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two‐stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre‐determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures‐of‐merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka‐band (26.5‐31.5 GHz) and K‐band (20.0‐24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka‐band and K‐band version. Input and output matching are typically better than 12 and 15 dB.     

Hybrid Ku‐band low‐noise amplifier for mobile DBS active phased‐array antennas

In this article we present a two‐stage Ku‐band low‐noise amplifier (LNA) using discrete pHEMT transistors on non‐PTFE substrates for low‐cost direct broadcast satellite (DBS) phased‐array systems (patent pending). The vertical input configuration of the LNA lends itself to direct integration with input port of antenna modules of the phased array, which minimizes preamplification losses. DC decoupling between LNA stages is realized using interdigital microstrip capacitors such that the implementation reduces the number of discrete microwave components and thereby not only reduces the component and assembly costs but also decreases the standard deviation of such crucial parameters of phased‐array systems as the end‐to‐end phase shift of the amplifier and the amplifier gain. Using the proposed printed decoupling capacitors, a cost reduction better than 30% of the original costs has been achieved. Additionally, we present a hybrid design procedure for the complete LNA, including its input and output connectors as well as packaging effects. This method is not based on parameter extraction, but encompasses electromagnetic (EM) field simulator results which are further combined using a high‐level circuit simulator. According to the presented measurement results, the implemented Ku‐band LNA has a noise figure better than 0.9 dB and a gain higher than 20 dB with a gain flatness of 0.3 dB over a 5% bandwidth. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

一种10GHz高增益低噪声放大器设计

提出了一种带有输入匹配网络优化方法的窄带10GHzLNA电路。通过插入全新的输入匹配网络,不仅满足LNA低噪声的要求,同时更使增益有所提高。提出的LNA采用0．181μmSiGeBiCMOS工艺,工作频率为10GHz。结果表明,提出的窄带HBT10GHzLNA电路,在10GHz频段测试增益大于lldB,噪声3．6dB,功耗9mw,达到了较好的匹配效果,有较好的稳定性,满足了收发机对LNA的指标要求。     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.