SOI／SDB薄膜全耗尽隐埋n—MOSFET导电机理研究

本文详细研究了SOI/SDB薄膜全耗尽隐埋n沟 MOSFET的器件结构及导电机理,建立了明确的物理解析模型,给出了各种状态下器件工作电流的解析表达式。最后,将解析模型的计算结果与实验数据进行了比较和讨论。     

Modeling of Surrounding Gate MOSFETs With Bulk Trap States

We report a simple analytical model for surrounding gate MOSFETs including bulk traps. Based on the depletion approximation and the assumption that bulk traps are uniformly distributed inside the bandgap, we solved Poisson's equation in cylindrical coordinates and derived the general solution of potential distribution. Extraction of threshold voltage and subthreshold slope were conducted. The analytical solution yields good agreement with MEDICI simulations confirming the model. The model predicts a linear threshold voltage drop, depending on the trap density, as the diameter of the device decreases when the channel is fully depleted     

SOI高压MOSFET的电流-电压特性模拟

在不同漂移区浓度分布下 ,通过二维数值模拟充分地研究了薄膜 SOI高压 MOSFET击穿电压的浓度相关性 ,指出了击穿优化对 MOSFET漂移区杂质浓度分布的要求。分析了MOSFET的电场电位分布随漏源电压的变化 ,提出寄生晶体管击穿有使 SOI MOSFET击穿降低的作用。     

双栅双应变沟道全耗尽SOI MOSFETs的特性分析

提出了一种全新的器件结构--双栅双应变沟道全耗尽SOI MOSFETs,模拟了沟道长度为25nm时器件的电学特性.工作在单栅模式下,应变沟道(Ge=0.3)驱动能力与体Si沟道相比,nMOS提高了43%,pMOS提高了67%;工作在双栅模式下,应变沟道(Ge=0.3)与体Si沟道相比较,驱动电流的提高nMOS为31%,pMOS为60%.仿真结果表明,双栅模式比单栅模式有更为陡直的亚阈值斜率,更高的跨导以及更强的抑制短沟道效应的能力.综合国内外相关报道,该结构可以在现今工艺条件下实现.     

Anodic Oxidation of Hydrogen-Transferred Silicon-on-Insulator Layers

Semiconductors - The anodic oxidation rate of silicon-on-insulator films fabricated by hydrogen transfer is studied as a function of the temperature of subsequent annealing. It is established that...     

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed     

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage     

Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrierluminescence techniques

This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions     

Subthreshold slope in thin-film SOI MOSFETs

The subthreshold conduction regime in thick- and thin-film SOI MOSFETs is studied. Using the depletion approximation, a one-dimensional analytical expression for the subthreshold slope is derived, and equivalence with a simple capacitive network is proven. The model accounts for the influence of the back interface properties on the subthreshold swing in the thin-film regime. The coupling between front and back surface potential and the influence of the backside conduction on the front interface characteristics are accounted for. The case of double gate control is studied in more detail. Experimental verification of the model with measured subthreshold slopes in thin-form MOSFET devices is given     

Linear dynamic self-heating in SOI MOSFETs

A model for small-signal dynamic self-heating is derived for the general case of a two-port device and then specialized to the case of an SOI MOSFET. The model is fitted to measured data for an SOI MOSFET and shown to accurately describe the frequency dependence of the self-heating. For this device, three time constants of 0.25 μs, 17 ns, and 90 ps adequately characterize the thermal response, showing that self-heating effects are active over a very wide frequency range     

Quantum-mechanical effects in trigate SOI MOSFETs

A self-consistent Poisson-Schro/spl uml/dinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm /spl times/ 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold voltage is higher than predicted by classical Poisson solvers. The current drive is diminished, and the subthreshold slope is degraded, especially in the devices with the smallest cross sections.     

Measurement of substrate current in SOI MOSFETs

A new “Quasi-SOI” MOSFET structure is shown to allow direct measurement of substrate current in a fully-depleted SOI device. The holes generated by impact ionization near the drain are collected at the substrate terminal after they have traversed the source-body barrier and caused bipolar multiplication. By monitoring this hole current, direct characterization of the impact-ionization multiplication factor, M, and the parasitic bipolar gain, β, was performed. It was found that M-1 increases exponentially with V_DS and decreases with V_GS, exhibiting a drain field dependence. The bipolar gain β was found to be as high as 1000 for V_GS-V_T=0 V and V_DS=-2.5 V, but decreases exponentially as V_DS increases. Finally, it was found that β also decreases as V_GS increases     

Numerical Study of C–V Characteristics of Double-Gate Ultrathin SOI MOSFETs

Capacitance-voltage (C-V) characteristics of double-gate ultrathin silicon-on-insulator (SOI) MOSFETs are numerically investigated in detail. The measured back-gate bias dependence is reproduced by the Poisson-Schrodinger solver including the highly precise physical models for many-body interactions of carrier-carrier and carrier-ion, and for incomplete ionization of doping impurities in whole semiconductor regions of n⁺poly-Si/oxide/SOI/oxide/p-Si capacitor including the volume inversion. In addition, we study the higher subband effect at higher temperature in detail, in order to deduce the impacts of self-heating and nonstatic transport     

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.     

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height Phi_B is found to strongly affect the threshold voltage V_th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t_OX and SOI body thickness; the contribution of inhomogeneity to the V_th variation becomes less pronounced with smaller t_OX and/or larger t_si . Moreover, an enhanced V_th variation is observed for devices with dopant segregation used for reduction of the effective Phi_B . Furthermore, a multigate structure is found to help suppress the V_th variation by improving carrier injection through reduction of its sensitivity to the Phi_B inhomogeneity. A new method for extraction of Phi_B from room temperature transfer characteristics is also presented.     

SOI MOSFET器件的热载流子退化机理

介绍了绝缭体上硅（SOI）材料的制作方法．阐进了SOIMOSFET器件的热载流子注入效应的失效机理。研究表明：前沟和背面缺陷的耦合效应是SOI器件的特有现象．对SOI器件的退化构成潜在的威胁。虽然失效机理比体硅器件复杂,但并不会阻碍高性能、低电压ULSI SOI电路的发展。     

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

Reduction of kink effect in thin-film SOI MOSFETs

Numerical simulation is used to show that potential and electric field distribution within thin, fully depleted SOI devices is quite different from that observed within thicker, partially depleted devices. Reduction of drain electric field and of source potential barrier brings about a dramatic decrease of kink effect     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction