GPS接收机载波跟踪环设计与分析

针对GPS接收机载波跟踪环环宽与跟踪的动态性能问题,在分析影响GPS信号动态性能的主要参数热噪声、晶振Allan相位噪声、晶振振动相位噪声和动态应力的基础上,通过对不同阶数的锁相环、锁频环跟踪门限分析与仿真,主要解决了如何设计GPS接收机的载波跟踪环路的带宽,并使系统性能达到最佳的问题,即使用环宽为18 Hz的二阶锁相环辅助环宽为10 Hz的三阶锁频环可以跟踪动态范围小于10 g、100 g/s的高动态信号。     

采用锁频环和锁相环联合捕获的载波跟踪

针对传统锁频环-锁相环跟踪算法中环路状态转换过渡中出现频率阶跃的问题,提出了一种采用锁频环和锁相环联合捕获的方式替代单一锁频环进行捕获的改进算法,同时对环路状态转换的门限进行了推导。仿真结果表明,改进的算法在转换过程中更加平稳,环路性能得到了优化。在信噪比为-10 dB且存在加加速度时跟踪环路在转换时没有出现频率阶跃,达到了设计目的。     

GPS软件接收机跟踪环路设计

GPS软件接收机跟踪环路的设计在环路参数与鉴相器选择上有很大空间。在分析GPS跟踪原理的基础上．对比码环与载波环不同鉴相器的性能,然后在不同环路参数下对跟踪效果进行了仿真比较,最后选择一组鉴相器并设计合适的环路参数,对实际采集的GPS中频信号进行跟踪,跟踪结果验证了设计环路的有效性。     

引入微分控制思想的辅助GPS载波跟踪环路设计

 载波信号跟踪环路制约着GPS接收机的工作性能,针对其易受高动态和弱信号等环境干扰的缺陷,提出一种引入微分控制思想、应用SINS辅助接收机载波跟踪环路的设计方法.剖析应用于载波跟踪的相位锁定环(Phase Locked Loop,PLL),并将其近似为PI控制模型;在验证辅助信息引入时环路系统稳定的基础上,增加类微分控制项,利用SINS的输出和时钟误差信息估算的多普勒频率作为跟踪环路的中心频率,辅助PLL实现载波信号跟踪;仿真结果表明提出方法能够有效地缩短跟踪环路带宽,缓解热噪声和动态应力之间的矛盾,进而改善载波环路的频率响应和跟踪误差.     

Time-domain Approach to the Performance Analysis of GPS Phase Locked Loop

The frequency-domain approach is widely used in Global positioning system (GPS) receiver track-ing loop performance analysis. In realization, the Digital phase-locked loop (DPLL) is used. There is difference be-tween phase errors by traditional frequency-domain analy-sis and real receiver output because of discretization errors. In order to get more precise result, this paper uses time-domain difference equations to analyze the phase tracking errors under the influence of thermal noise and the dy-namic stress on different orders of PLL. The simulation re-sults show that the traditional frequency-domain approach has phase error deviation under long integration time (i.e., more than 10ms), while the time-domain approach has good accordance with receiver simulation output. Thus, the proposed time-domain approach can provide more pre-cise solution for PLL performance analysis.     

一种针对压缩域信号的新型锁相环技术

针对通信信号压缩采样获得的压缩域信号频率、相位提取问题,提出了一种基于压缩感知的新型锁相环技术。通过深入研究压缩域的信号估计问题,提出了压缩域锁相环路,可以直接在压缩域同步跟踪信号频率和相位变化,不再需要高复杂度的信号重构处理。分析了环路模型及其估计性能,并针对该锁相环可行性和性能分别进行了仿真实验。仿真结果不仅验证了压缩域锁相环的可行性,同时表明该环路能够实现高动态信号的高精度频率提取。压缩域锁相环的应用潜力较大,例如可以作为压缩感知通信接收机的同步解调方法。     

基于GPS技术进行精确授时的方法

本文研究了GPS精确授时系统结构以及静态和动态环境下进行精确授时的方法.在静态环境下,利用伪距和载波相位进行授时,我们通过仿真得出了使用这种方法的授时精度.在动态环境下,GPS信号发生失锁现象会导致授时精度大大降低,使用秒脉冲和高精度晶振进行精确授时可以大大提高高动态情况下的授时精度,我们通过仿真分析了使用高精度晶振辅助授时对精度的影响.     

基于改进粒子滤波的GPS接收机自主完好性监测算法

针对基本粒子滤波重采样过程中粒子权值退化和多样性丧失的问题,将遗传算法引入基于神经网络的权值调整粒子滤波算法中,结合了遗传算法全局寻优的收敛性与神经网络局部寻优的快速性优点。将提出的算法与对数似然比方法结合用于GPS接收机自主完好性监测,通过建立一致性检验统计量实现对故障卫星的检测与隔离。通过采集实测数据进行验证,结果表明:该算法可以成功检测和隔离故障卫星,其性能优于基于基本粒子滤波的接收机自主完好性监测,验证了该算法应用于GPS接收机自主完好性监测的可行性和有效性。     

多路微波电视传输系统的设计

概述了多路微波电视传输系统的特点，介绍了此系统的总体设计及各部分的工作原理。     

基于DDS技术L波段小步进低相噪频率源设计与实现

将DDS技术应用于超短波射频通信频率源中,比较了几种常见的小步进频率源的设计方案,设计实现了一种"锁相环-直接数字频率合成器-锁相环"(PLL+DDS+PLL)结构的高性能频率源。与传统的频率源设计相比,新的设计更能够满足工程应用过程中小步进、低相噪、高集成度的需求;设计频率源输出频率范围为1 766.5~1 771.5 MHz,步进0.000 5 Hz,相位噪声在距输出频率10 k Hz处小于–95 d Bc,杂散抑制度优于70 d Bc。     

A Novel Dual‐Mode Bandpass Filter Based on a Defected Waveguide Resonator

A novel dual‐mode bandpass filter (BPF) using a dual spiral‐shaped defected ground waveguide (DGW) resonator is proposed in this letter. The dual‐mode characteristic of this filter is achieved by loading a defected T‐shaped stub at the midline of the spiral‐shaped DGW resonator. Also, non‐orthogonal input and output feed‐lines are adopted in the filter. Based on the compact DGW structure, a dual‐mode BPF with central frequency of 1.5 GHz for the global positioning system is designed, fabricated, and measured. Measured results agree well with the predicted response and verify the proposed methodology.     

SC-FDE宽带航空数传接收机的设计与实现

为满足航空信道条件下的远距离宽带数据传输需求,基于单载波频域均衡传输(SC-FDE)体制,采用8 PSK调制体制进行了宽带数字接收机的设计,包括传输帧同步、载波同步、定时同步、信道估计和频域均衡.同时,为保证灵活应用的需求,采用数字内插的方式进行了可变传输速率设计.基于Xilinx现场可编程门阵列(FPGA)平台对硬件实现进行优化,最终实现了传输速率能够从112.5 Mbit/s覆盖到900 Mbit/s的数传接收机.仿真分析和硬件测试结果表明,该接收解调设备能够实现很好的性能指标,同时SC-FDE架构具备有效补偿多径传播影响的能力,适合应用于高动态无线宽带航空数据传输系统中.     

Improved Delay‐Locked Loop in a UWB Impulse Radio Time‐Hopping Spread‐Spectrum System

As ultra‐wideband impulse radio (UWB‐IR) uses short‐duration impulse signals of nanoseconds, even a small number of timing errors can cause a detrimental effect on system performance. A delay‐locked loop (DLL) is proposed to synchronize and reduce timing errors. The design of the DLL is vital for UWB systems. In this paper, an improved DLL is introduced to a UWB‐IR time‐hopping spread‐spectrum system. Instead of using only two central correlator branches as in a conventional DLL, the proposed system uses two additional correlator branches with different delay parameters and different weight parameters. The performance of the proposed schemes with the optimal parameters is compared with that of traditional schemes through simulation: the proposed four‐branch DLLs achieves less tracking jitter or a longer mean time to lose lock (MTLL) than the conventional two‐branch DLLs if proper parameters are chosen.     

Clock synchronization for packet networks using a weighted least‐squares error filtering technique and enabling circuit emulation service

Circuit emulation service (CES) allows time‐division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase‐locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state. Copyright © 2006 John Wiley & Sons, Ltd.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

Low peak‐to‐average power ratio and efficient multicarrier spread spectrum transceivers using hybrid and quadrature cyclic shift orthogonal keying

This paper proposes two bandwidth and power efficient multicode multicarrier spread spectrum (MCSS) system modes based on a new cyclic shift orthogonal keying (CSOK) scheme that leads to low peak‐to‐average power ratio (PAPR) signals. Both system modes can improve the bandwidth efficiency by loading more data bits per symbol block. The first system mode is the hybrid CSOK (HCSOK) mode, which combines phase shift keying (PSK) or quadrature amplitude modulation (QAM) modulation symbol with the CSOK symbol, for example, the important hybrid quadrature PSK (QPSK)–CSOK case. The second is the quadrature CSOK (QCSOK) mode that transmits two parallel binary phase shift keying (BPSK)–CSOK branches at the same time. For both modes, maximum likelihood receivers are derived and simplified, leading to efficient fast Fourier transform‐based structures for maximum ratio combining and cyclic‐code correlation. Theoretical bit error rate (BER) analysis is conducted for the hybrid QPSK–CSOK case. Simulation results demonstrate that both the two system modes considerably outperforms the traditional Walsh‐coded MCSS system in terms of bandwidth efficiency, PAPR, BER, and antijamming capability. Furthermore, in indoor channel, QCSOK performs slightly worse than QPSK–CSOK, but it has almost twice the data rate when the code length is large. Copyright © 2011 John Wiley & Sons, Ltd.