钟控密钥流生成器及其密码性能

提出了一种新的钟控密钥流生成器,由3个移位寄存器组成：两个被钟控的线性反馈移位寄存器A和B,一个提供钟控信息的非线性反馈移位寄存器C。设A、B和C的长度分别为l1、l2和l3。移位寄存器A和B的钟控信息由从移位寄存器C选取的两个比特串提供,移位的次数分别是两个比特串的汉明重量。研究了该生成器的周期、线性复杂度和k错线性复杂度,分析了这种密钥流生成器的安全性。     

Transform decoding of BCH codes over Zm

For BCH codes with symbols from rings of residue class integers modulo m, denoted by Z_m , we introduce the analogue of Blahut's frequency domain approach for codes over finite fields and show that the problem of decoding these codes is equivalent to the minimal shift register synthesis problem over Galois rings. A minimal shift register synthesis algorithm over Galois rings is obtained by straightforward extention of the Reeds-Sloane algorithm which is for shift register synthesis over Z_m .     

A generalization of the Berlekamp-Massey algorithm formultisequence shift-register synthesis with applications to decodingcyclic codes

A generalization of the Berlekamp-Massey algorithm is presented for synthesizing minimum length linear feedback shift registers for generating prescribed multiple sequences. A more general problem is first considered, that of finding the smallest initial set of linearly dependent columns in a matrix over an arbitrary field, which includes the multisequence problem as a special case. A simple iterative algorithm, the fundamental iterative algorithm (FIA), is presented for solving this problem. The generalized algorithm is then derived through a refinement of the FIA. Application of this generalized algorithm to decoding cyclic codes up to the Hartmann-Tzeng (HT) bound and Roos bound making use of multiple syndrome sequences is considered. Conditions for guaranteeing that the connection polynomial of the shortest linear feedback shift register obtained by the algorithm will be the error-locator polynomial are determined with respect to decoding up to the HT bound and special cases of the Roos bound     

一种新的MPEG音频解码方案及算法优化

设计了一种新的MPEG音频解码框架.输入音频数据不需经过串行化,通过桶型移位器组织数据读取,提高了解码效率.解码器针对硬件处理特性设计了专用比特流输入单元和解组处理单元.对运算瓶颈子带滤波器设计了优化算法,使运算量降低为标准算法的1/4左右,存储空间降低为原来的1/2.该方案可用于DVB和DAB信源解码芯片中.     

Multisequence Linear Shift Register Synthesis and Its Application to BCH Decoding

This concise paper demonstrates the decoding of BCH codes by using a multisequence linear feedback shift register (MLFSR) synthesis algorithm. The algorithm is investigated and developed. With this algorithm, a class of good codes has been found with errorcorrecting capability at least as good as the BCH bound. The application of this algorithm to BCH decoding is discussed.     

Memory savings in Viterbi decoders for (n, 1, m) convolutional codes

A novel approach to achieve memory savings in MLD Viterbi decoders is proposed. It is based on tracking a code's trellis survivor paths in the decoding decision process using a backward labels technique, rather than the traditional forward labels technique, and exploiting a shift register property of the trellis. Savings of the order of 20% of memory requirements in (n, 1, m) convolutional codes are achievable without loss of decoding performance.     

Shift-register synthesis and BCH decoding

It is shown in this paper that the iterative algorithm introduced by Berlekamp for decoding BCH codes actually provides a general solution to the problem of synthesizing the shortest linear feedback shift register capable of generating a prescribed finite sequence of digits. The shift-register approach leads to a simple proof of the validity of the algorithm as well as providing additional insight into its properties. The equivalence of the decoding problem for BCH codes to a shift-register synthesis problem is demonstrated, and other applications for the algorithm are suggested.     

CCD memory using multilevel storage

In CCD multilevel storage, more than one bit of information is stored in a charge packet. Requirements for CCD MLS systems are described, and circuits for the encoding and decoding of charge packets which operate essentially independent of device parameter and geometric tolerances are presented. 3-bit operation on a short shift register loop is demonstrated. Requirements on leakage and transfer in efficiency for 2- and 3-bit MLS are discussed.     

A New Attack on the Filter Generator

The filter generator is an important building block in many stream ciphers. The generator consists of a linear feedback shift register of length n that generates an m-sequence of period 2ⁿ-1 filtered through a Boolean function of degree d that combines bits from the shift register and creates an output bit z_t at any time t. The previous best attacks aimed at reconstructing the initial state from an observed keystream, have essentially reduced the problem to solving a nonlinear system of D=Sigma_i=1 ^d(n/i) equations in n unknowns using techniques based on linear algebra. This attack needs about D bits of keystream and the system can be solved in complexity O(D^omega), where omega can be taken to be Strassen's reduction exponent omega=log₂(7)ap2.807. This paper describes a new algorithm that recovers the initial state of most filter generators after observing O(D) keystream bits with complexity O((D-n)/2)apO(D), after a pre-computation with complexity O(D(log₂D)³)     

一种新型的turbo码LOG-MAP译码算法

给出了一种新型的turbo码LOC-MAP译码算法，相对于传统的LOG-MAP译码算法，主要有两点创新。其一，对于LOC-MAP算法中的校正函数采用三阶Newton插值函数拟合，相对于分段线性函数拟合，省去了查找表过程和查找表的存储；其二，相对于传统的单滑动窗口技术，采用双滑动窗口技术，对于前向递归和后向递归分别采用滑动窗口技术，同时采用预处理技术，这样显著地提高了译码速度。     

On type-B1 burst-error-correcting convolutional codes

Two new classes of type-B1 burst-error-correcting convolutional codes are introduced. One of them requires a shorter length of guard space and a smaller number of shift register stages than optimum type-B2 codes used for type-B1 burst correction. Another class of codes improves the required number of shift register stages considerably when the correctable burst length is very large. In addition, these codes require a very short length of additional guard space to restore the decoder to correct operation after a decoding failure. Both classes of codes are derived in a straightforward manner and their implementations are also very simple. Thus, we can avoid type-B2 code procedures to correct type-B1 bursts. The codes derived here result in the more efficient and simply implemented type-B1 burst-correcting convolutional codes.     

准循环低密度校验码的构造

文中提出了一种利用筛选算法寻找指数矩阵的新方法,其构造的准循环低密度校验码有两个主要的优点:一是可用简单线性移位寄存器完成编码;二是只需存储校验矩阵的指数矩阵,可节约很多存储空间.利用计算机能较快的搜索圈长为的循环置换矩阵阶数的最小值,搜出的这些在理论上达到了Fossorier给出的最小下界.仿真结果表明构造的低密度校验码在加性高斯白噪声信道中BPSK调制下用和积迭代译码算法的误比特性能表现良好.     

On the decoding of Reed-Solomon and BCH codes over integer residuerings

We present a decoding procedure for Reed-Solomon (RS) and BCH codes defined over an integer residue ring pgZ_q, where q is a power of a prime p. The proposed decoding procedure, as for RS and BCH codes over fields, consists of four major steps: (1) calculation of the syndromes; (2) calculation of the “elementary symmetric functions,” by a modified Berlekamp-Massey (1968, 1969) algorithm for commutative rings; (3) calculation of the error location numbers; and (4) calculation of the error magnitudes. The proposed decoding procedure also applies to the synthesis of a shortest linear-feedback shift register (LFSR), capable of generating a prescribed finite sequence of elements lying in a commutative ring with identity     

A generalized Euclidean algorithm for multisequence shift-registersynthesis

The problem of finding a linear-feedback shift register of shortest length capable of generating prescribed multiple sequences is considered. A generalized Euclidean algorithm, which is based on a generalized polynomial division algorithm, is presented. A necessary and sufficient condition for the uniqueness of the solution is given. When the solution is not unique, the set of all possible solutions is also derived. It is shown that the algorithm can be applied to the decoding of many cyclic codes for which multiple syndrome sequences are available. When it is applied to the case of a single sequence, the algorithm reduces to that introduced by Y. Sugiyama et al. (Inf. Control, vol.27, p.87-9, Feb. 1975) in the decoding of BCH codes     

Two step SOVA-based decoding algorithm for tailbiting codes

In this work we propose a novel decoding algorithm for tailbiting convolutional codes and evaluate its performance over different channels. The proposed method consists on a fixed two-step Viterbi decoding of the received data. In the first step, an estimation of the most likely state is performed based on a SOVA decoding. The second step consists of a conventional Viterbi decoding that employs the state estimated in the previous step as the initial and final states of the trellis. Simulations results show a performance close to that of maximum-likelihood decoding.     

二元给定序列非线性移位寄存器的综合与产生

依据非线性移位寄存器的原理，文中讨论二元给定序列非线性反馈移位寄存器的综合算法，用C语言编程．找到了产生该序列的非线性移位寄存器。借助EDA技术，以FPGA为硬件基础，经过设计优化构成定长序列和给定周期序列的伪随机序列发生器，并进行了仿真实验，用硬件实验证实了设计的合理性。     

Multisequence shift register synthesis over commutative rings with identity with applications to decoding cyclic codes over integer residue rings

We present a new algorithm for solving the multisequence shift register synthesis problem over a commutative ring R with identity. Given a finite set of R-sequences, each of length L, the complexity of our algorithm in terms of R-multiplications is O(L/sup 2/) as L /spl rarr/ /spl infin/. An important application of this algorithm is in the decoding of cyclic codes over Z/sub q/ up to the Hartmann-Tzeng bound, where q is a prime power. Characterization of the set of monic characteristic polynomials of a prescribed set of multiple syndrome sequences leads to an efficient decoding procedure, which we further extend to decode cyclic codes over Z/sub m/ where m is a product of prime powers.     

(2,1,7)卷积码Viterbi译码器FPGA实现方案

移动通信系统标准中普遍采用卷积码作为信道编码方案。本文阐述了目前最常用的卷积码译码算法——Vit-erbi译码算法,然后给出了(2,1,7)卷积码编码电路FPGA实现方法。该方法给出了新的Viterbi幸运路径算法和高效的状态度量存储技术,可以充分利用FPGA的优势获得较好的译码结果。利用幸存路径交换寄存器模块,能有效减少存储量并降低功耗。