Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Structural and electrical properties of furnace and rapid thermallyannealed LPCVD WSi2 films on single-crystal, polycrystalline,and amorphous silicon substrates

Alternate approaches to obtain low-resistance, low-pressure chemical vapor deposition (LPCVD) WSi₂ films for application as interconnections in silicon integrated circuit technologies were investigated. The silicide films were deposited on three different substrates and annealed in two different systems. The silicide films deposited on the doped substrates as well as films doped using ion implantation were analyzed. The silicide microstructure, electrical film conductivity, and dopant redistribution were studied as a function of the process variants. An optimum set of annealing conditions were identified that resulted in excellent silicide thin-film properties. A correlation between the material and electrical properties is provided using the experimental data     

快速热处理对PECVD氮化硅薄膜性能的影响

利用PECVD在硅片上沉积了氮化硅(SiNx)薄膜,将沉积膜后的样品放在N2气氛中进行快速热处理(RTP),研究了不同快速热处理对PECVD氮化硅薄膜件能的影响.采用原子力显微镜(AFM)检测薄膜的表面形貌,利用椭圆偏振仪测量样品膜厚和折射率,利用准稳态光电导衰减法(QSSPCD)测鼋样品的少子寿命.实验结果表明随着RTP温度的升高,薄膜厚度迅速减小,折射率迅速增大;低于500℃热处理时,少子寿命基本不变;高于500℃热处理时,随着温度的升高,少子寿命急剧下降.氮化硅薄膜经热处理后反射率基本不变.     

The electrical properties of sub-5-nm oxynitride dielectricsprepared in a nitric oxide ambient using rapid thermal processing

Ultrathin (<5 nm) dielectric films have been grown on 〈100〉 silicon using rapid thermal processing (RTP) in a nitric oxide (NO) ambient. Interface state density, charge trapping properties, and interface state generation during Fowler-Nordheim electron injection have been investigated. The films grown in NO have excellent electrical properties. These properties are explained in terms of a much stronger and large number of Si-N bonds in both the bulk of the dielectric films and at the Si-SiO₂ interface region. The leakage currents are at least three orders of magnitude lower than other reported results for similar thicknesses. The dielectric films grown in NO ambient are viewed as promising technology for ultrathin dielectrics     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Titanium silicide-silicon interface degradation during heat treatment

Thin titanium silicide films were grown on different silicon substrates by rapid thermal annealing in a nitrogen ambient. The silicide films were then annealed in a furnace at high temperature in a nitrogen ambient for various times. The effect of such heat treat-ment on the morphology of titanium silicide surface and the titanium silicide-silicon interface was studied. It is proposed that the morphological change is primarily due to the diffusion of silicon and/or dopant impurities via grain boundaries of the silicide. There is a strong correlation between the surface of the titanium silicide film and that of the titanium silicide-silicon interface.     

Selective deposition of TiSi2 on oxide patterned wafers using low pressure chemical vapor deposition

The selective deposition of titanium disilicide was investigated using a cold-wall, low pressure chemical vapor deposition (LPCVD) technique with silane and titanium tetrachloride as the silicon and titanium sources, respectively. In-situ hydrogen plasma effectively cleaned the silicon wafer surface for deposition of C54 TiSi₂ at 760‡ C with full selectivity. A new method using a plasma only at the beginning of the deposition of the silicide further decreased the temperature to 680‡ C without losing selectivity. The result was a fine grained film probably due to the enhanced nucleation rate of the silicide. Cross-sectional TEM studies showed that the silicide grew into the silicon substrate, suggesting significant silicon consumption. The silicon substrate, consequently, seems to play a major role in the silicide formation. Silane, on the other hand, plays a minor role as a silicon source but does act as a scavenger of HC1 in the gas or on the silicide surface.     

Using wavelength-dependent emissivity of semiconductor wafer tomodel heat transfer in rapid thermal processing station

This paper develops an approach for using a wavelength-dependent emissivity model of a semiconductor wafer in calculating heat transfer in a rapid thermal processing (RTP) station. The wafer emissivity is modeled by a generalized polynomial in wavelength where the coefficients may be functions of temperature. A comparison of experimental data with simulated results for a silicon wafer is provided     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Process uniformity and slip dislocation patterns in linearlyramped-temperature transient rapid thermal processing of silicon

Rapid thermal processing (RTP) of silicon using transient linearly ramped-temperature saw-toothed and triangular thermal cycles has been evaluated by characterization of the process uniformity and slip dislocation line patterns for a wide range of process parameters. Rapid thermal oxidation was chosen as the process vehicle for these studies. The process uniformity and slip dislocation line patterns are strongly affected by both the transient and steady-state segments of the thermal cycles. The strong dependencies of the process uniformity and slip dislocation lines on the thermal cycle parameters suggest that the overall performance of a RTP reactor must be specified not only under steady-state thermal conditions, but also for controlled transient thermal cycles. Transient ramped-temperature RTP cycles with medium-to-high peak process temperatures (i.e. T_max=1100°-1150°C) were found to be the optimal process conditions for growing thin gate oxides in the range of 60-120 Å with superior process uniformity and minimum slip dislocation line generation. The results of this work provide insight and useful methodology for process optimization in order to improve process uniformity, minimize generation of slip dislocation lines, and obtain good device electrical characteristics     

Annealing-temperature dependence of the thermal conductivity ofLPCVD silicon-dioxide layers

The authors point out that the reliability and performance of electronic circuits are influenced by heat conduction in low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide layers. Here, the effective thermal conductivity k_eff for conduction normal to films of LPCVD silicon dioxide layers as a function of annealing temperature, as well as for films of thermal and SIMOX oxides, is measured. The LPCVD oxide thermal conductivity increases by 23% due to annealing at 1150°C. The conductivities k_eff of LPCVD layers of thicknesses between 0.03 and 0.7 μm are higher than those reported previously for CVD layers, and vary between 50% and 90% of the conductivities of bulk fused silicon dioxide. The values of SIMOX and thermal oxide layers are within the experimental error of the values for bulk fused silicon dioxide     

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi₂ were possible for thicker films depending on anneal temperature and time. Activation energy of 2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi₂ is higher than for morphological degradation.     

大直径直拉硅片的快速热处理

主要研究了快速热处理( RTP)对大直径直拉( CZ)硅片的清洁区( DZ)和氧沉淀的影响.通过在Ar、N2 、O2 三种不同气氛中,在不同温度下RTP发现在大直径CZ硅片中氧沉淀的行为及DZ的宽度与RTP的温度、气氛有很大关系.在实验的基础上,讨论了在大直径CZ硅中RTP对氧沉淀和DZ的影响机理.     

Rapid thermal annealing of high-melting-point films onlow-melting-point substrates

Rapid thermal annealing which involves fast heating and cooling rates, is used to activate dopants in thin-film structures yet minimize the dopant diffusion that occurs with excessive thermal exposure. Although the proper resulting electrical properties are the main concern, the structural behavior must also be considered. At the elevated annealing temperature, the heterostructure may be susceptible to both relaxation and yielding. However, the relative effect of these deformations is a function of the material properties, ramp-rate, annealing conditions, and wafer geometry, In particular, for a high-melting-point film on a lower-melting-point substrate, the substrate will experience the inelastic effects prior to the film. More specifically, because germanium has a significantly lower melting point than silicon, previously developed processing technology for silicon cannot be applied directly to germanium processing. A numerical model has been developed to account for the thermo-mechanical effects associated with rapid thermal annealing of relaxing materials. Numerical parametric studies have been conducted for rapid thermal annealing of a thin polysilicon film on a (111) germanium substrate in order to determine the optimum processing window. Results reveal that lower annealing temperatures that still fall within the RTA regime will minimize or even eliminate the plastic damage that could occur during thermal processing     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

Uniform durable thin dielectrics prepared by rapid thermalprocessing in an N2O ambient

Thin dielectrics grown on silicon wafers by rapid thermal processing in an N₂O ambient at temperatures of 1100°C, 1150°C, and 1200°C are discussed. The resulting films, in conjunction with an O₂ ambient control were characterized by thickness measurements and electrical performance. Dielectrics formed in N₂O in this temperature range were all superior to that prepared in an O₂ ambient in terms of interface state generation and flatband voltage shift after constant current stressing. Although all N₂O prepared samples exhibited similar cross wafer electrical uniformity, higher growth temperatures favored thickness uniformity. The electrical behavior of the N₂O wafers was not strongly dependent on growth temperature; however, a 60-s 1100°C post-oxynitridation N₂ anneal was found to significantly reduce subsequent electrical performance. It is also demonstrated that under optimum process conditions, high-quality uniform dielectrics can be formed by RTP in N₂O     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Effect of rapid thermally nitrided titanium films contacting silicided and nonsilicided junctions

The effect of rapid thermally nitrided titanium films contacting silicided (titanium disilicided) and nonsilicided junctions has been studied in the temperature range of 800 to 900°C. The rapid thermal nitridation of titanium films used as diffusion barriers between aluminum and silicon, has a major impact on shallow junction complementary metal oxide semiconductor technologies. During the process of rapid thermal nitridation, the dopants in the junctions undergo a redistribution and affect the electrical properties of shallow junction structures. This work focuses on using novel contact resistance structures to measure the variation in electrical parameters for rapid thermally nitrided titanium films annealed at different temperatures. The self-aligned silicide (salicide) junctions in this study were formed using rapid thermally annealed titanium films. Electrical contact resistance testers were used to measure the interface contact resistance between the salicide and silicon, as well as between the metal and the salicide. The results show that the interface contact resistance to the p⁻ diffused salicided junctions increases with rapid thermal nitridation of the additional titanium film, whereas the interface contact resistance to the n⁻ diffused salicided junction shows a decrease. Further, as a function of the rapid thermal annealing temperature (for fixed titanium thickness), the nonsalicided diffusions show an increase in the interface contact resistance. The boron profiles at the TiSi₂/Si interface obtained using secondary ion mass spectroscopy show an excellent qualitative agreement with the electrical results for each of the conditions discussed. The films were also characterized using Rutherford back-scattering spectrometry and transmission electron microscopy and the results show good agreement with the measured variation in electrical parameters. These results also show that as the anneal temperature is increased, the TiN thickness increases, further the change in the silicide/silicon interface position with the nitridation of the additional titanium layer was verified. This work was carried out when the author was working at AT&T Bell Labs     

快速热处理对重掺As硅单晶中氧沉淀的影响

对重掺As硅片进行快速热处理，发现重掺As硅片中氧沉淀行为与快速热处理温度、保温时间和降温速度有很大的关系. 随着快速热处理温度的升高、降温速度的增大和保温时间的延长，氧沉淀的密度增大. 最后对影响的机理进行了讨论.