一种10位高速Pipeline-SAR混合型ADC设计

基于180 nm CMOS工艺,设计了一种无残差放大的10位100 MS/s流水线与逐次逼近混合型ADC。采用两级流水线-逐次逼近混合型结构,第一级完成4位粗量化转换,第二级完成6位细量化转换。为了降低整体电路功耗,采用单调式电容控制切换方式,两级之间残差电压采用采样开关电荷共享方式实现。采用异步时序控制逻辑,进一步提升了能量利用率和转换速度。后仿真结果表明,在100 MS/s奈奎斯特采样率下,有效位数为9.39 bit,信噪失真比为58.34 dB,1.8 V电源电压下整体功耗为5.9 mW。     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.     

一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit,100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D,电容值为1fF的MOM电容。除此之外,改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性,该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s,输入频率1MS/s时,有效位数（ENOB）为7.4,bit,信噪失真比（SNDR）为46.40dB,无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2,在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。     

An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

An 8-b 100-MS/s pipelined analog-to-digital converter(ADC) is presented.Without the dedicated sample-and -hold amplifier(SHA),it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,respectively.The closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power optimization.The theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the...     

一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration

Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4 and 10.7 , respectively, compared to a 14 bit uncalibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18 um CMOS process occupies an active die area of 4.2 mm² and consumes 140 mW at 1.8 V and 50 MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69 to 0.39 LSB and from 33.60 to 2.76 LSB, respectively.     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

一种12位80 MS/s CMOS流水线ADC设计

介绍了一种12 bit 80 MS/s流水线ADC的设计,用于基带信号处理,其中第一级采用了2.5 bit级电路,采样保持级采用了自举开关提高线性,后级电路采用了缩减技术,节省了芯片面积.采用了折叠增益自举运放,优化了运放的建立速度,节省了功耗.芯片采用HJTC0.18μm标准CMOS工艺,1.8 V电压供电,版图面积2.3 mm × 1.4 mm.版图后仿真表明,ADC在8 MHz正弦信号1 V峰值输入下,可以达到11.10 bit有效精度,SFDR达到80.16 dB,整个芯片的功耗为155 mW.     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

一种10位50MS/s两级逐次逼近流水线混合型A/D转换器

本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器（pipeline SAR ADC）。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.     

一个低电压低功耗10位30MS/s流水线A/D转换器

实现了一个10位精度,30MS/s,1.2V电源电压流水线A/D转换器,通过采用运放共享技术和动态比较器,大大降低了电路的功耗。为了在低电源电压下获得较大的摆幅,设计了一个采用新颖频率补偿方法的两级运放,并深入分析了该运放的频率特性。同时还采用了一个新的偏置电路给运放提供稳定且精确的偏置。在30MHz采样时钟,0.5MHz输入信号下测试,可以得到8.1bit有效位的输出,当输入频率上升到60MHz(四倍奈奎斯特频率)时,仍然有7.9bit有效位。电路积分非线性的最大值为1.98LSB,微分非线性的最大值为0.7LSB。电路采用0.13μmCMOS工艺流片验证,芯片面积为1.12mm2,功耗仅为14.4mW。     

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

A 1.4-V 25-Mw 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30. 1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm~2 in the 0.13-μm CMOS process.     

一种高速高精度采样/保持电路

介绍了一种用于12bit,100MS/s流水线模数转换器前端的采样/保持电路的设计.该电路在3V电源电压100MHz采样频率时,输入直到奈奎斯特频率仍能够达到108dB的无杂散动态范围(SFDR)和77dB的信躁比(SNR).论文建立了考虑开关之后的采样保持电路的分析模型,并详细研究了电路中开关组合对电路性能的影响,同时发现了传统的栅源自举开关(bootstrapped switch)中存在的漏电现象并对其进行了改进,极大地减小了漏电并提高了电路的线性性能.     

用于14位210 MS/s电荷域ADC的4.5位子级电路

该文提出了一种用于高速高精度电荷域流水线模数转换器(ADC)的电荷域4.5位前端子级电路。该4.5位子级电路使用增强型电荷传输(BCT)电路替代传统开关电容技术流水线ADC中的高增益带宽积运放来实现电荷信号传输和余量处理,从而实现超低功耗。所提4.5位子级电路被运用于一款14位210 MS/s电荷域ADC中作为前端第1级子级电路,并在1P6M 0.18 μm CMOS工艺下实现。测试结果显示,该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc,信噪比为71.5 dBFS, ADC内核面积为3.2 mm2,功耗仅为205 mW。     

A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS

A 12-bit pipeline ADC fabricated in a 0.18-/spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2V/sub P-P/ signal swing is applied. The occupied silicon area is 0.86 mm/sup 2/ and the power consumption equals 97 mW. A switched capacitor bias current generator scales the opamp bias currents automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.