A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V     

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.     

A 64-kbit dynamic MOS RAM

A 64-kbit dynamic MOS RAM is developed by using 2 /spl mu/m rule VLSI fabrication technology and low power circuit technology. The 2 /spl mu/m rule VLSI fabrication technology is achieved by improving various aspects of the ultraviolet photolithographic, thin-gate oxidation, arsenic ion implantation, and multilevel interconnection processes. Microminiaturization of the device structure has made the voltage requirements for its MOST threshold voltage and DC supply voltages low. A highly sensitive and low power dissipating sense circuit has been developed for the VLSI RAM. A new level-detecting circuit with a logic threshold which is independent of MOST threshold voltage is proposed. A dynamic address-buffer circuit is also shown. The fabricated 64K RAM has 200 ns of access time, 370 ns of minimum cycle time, and 150 mW of power dissipation under typical supply voltage conditions of V/SUB DD/=7 V and V/SUB BB/=-2 V.     

DSA 4K static RAM

A high-performance diffusion self-aligned (DSA) 4K static RAM, which operates on a single power supply of 5 V without any clock input, has been fabricated. The RAM, composed of DSA MOSTs, depletion MOSTs, and high-impedance polysilicon load resistors, was designed using nonclocked static circuit techniques. The memory cell size and the chip size are 45/spl times/40 /spl mu/m and 3.88/spl times/3.45 mm, respectively. A typical access and cycle time of 76 ns is realized at a power dissipation of 500 mW. The RAM can retain data in a standby mode with a reduced supply voltage of 1.5 V, thereby decreasing the power dissipation to 60 mW. The active power dissipation can be decreased in a RAM fabricated with a lower ion-implantation dose to the depletion load MOSTs; thus the RAM may also be useful for memory applications where low power dissipation is of primary importance.     

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.     

Design and analysis of high-speed random access memory with Coulombblockade charge confinement

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns. The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors     

GaAs 1 kbit static RAM with self-aligned FET technology

A GaAs-1 kbit RAM is demonstrated to realize high-speed switching at the LSI level. The SAINT FET is utilized to eliminate the surface depletion without an increase of excess capacitance. To lower the threshold voltage standard deviation, a one-direction gate arrangement is adopted. A pull-up circuit is also a new addition to the first reported RAM. The resulting RAM performances are 1.5 ns address access time with 369 mW power consumption. The minimum write-enable pulsewidth is less than 2 ns. The maximum number of good bits is 1001 bits/1024 bits. The problems of mass production of GaAs LSI are discussed.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0× 10¹⁷ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor     

A three-dimensional static RAM

A three-dimensional (3-D) 256-bit static random-access memory (RAM) with double active layers has been fabricated by using the laser recrystallization technique. Memory cells were located in a bottom active layer with an NMOS configuration and peripheral circuits were arranged in a top active layer with a CMOS configuration. Both active layers were connected by 112 via holes. The chip and cell sizes were 2.6 × 1.9 mm²and 50 × 70 µm², respectively. The memory operation was observed with a supply voltage from 4 to 8 V. The shortest address access time of 42 ns was obtained at the supply voltage of 8 V.     

A 64K/spl times/1 bit dynamic ED-MOS RAM

A 64K/spl times/1 bit dynamic RAM based on an innovative short channel ED-MOS process technology and an improved ED-MOS sense amplifier circuit has been realized. The RAM has been designed by using 2-3 /spl mu/m design rules and employing ED-MOS peripheral circuits capable of low supply voltage operation. As a result, dynamic memory operation has been demonstrated with an access time less than 140 ns and a cycle time of 350 ns, using a single 5 V power supply.     

A flexible multiport RAM compiler for data path

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b×2048 words and 72 b×512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

HMOS III technology

A third-generation single-poly high-performance NMOS technology has been developed. The technology features scaled MOS devices with 250 /spl Aring/ gate and 0.25 pJ speed-power product. The technology integrates advanced processing capabilities in lithography and dry etching to achieve a depletion-load static memory cell size of 0.98 mils/SUP 2/. A 4K static RAM test vehicle has been fabricated with sub-15 ns access time. The technology has a major application in the shrink of existing microcomputers designed on previous HMOS technologies.     

A 209 K-transistor ECL gate array with RAM

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V/sub cc/ power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.<>     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

A 256K dynamic RAM with page-nibble mode

A 5-V 256K /spl times/ 1 bit NMOS dynamic RAM with page-nibble mode is designed and fabricated using 2-/spl mu/m design rules and folded bit-line configuration. Molybdenum disilicided polysilicon is used as the second-level gate to reduce the word-line signal delay. A large 98 /spl mu/m/SUP 2/ cell with Hi-C structure stores the signal charge of 210 fC and provides this memory with wide operating margin. The device is immune to voltage bumping and uses laser programmable redundancy. Typical RAS/CAS access times are 80 ns/40 ns. An average operating current of 50 mA with 80 mA peak at 230 ns cycle time and standby current of 2 mA are achieved.     

A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture

A 1-Mb dynamic RAM has been fabricated using 1.2-/spl mu/m double-level metal CMOS technology. A novel divided bitline matrix architecture allows the conventional double-polysilicon planar memory cell to be used without sacrificing signal-to-noise (S/N) ratio or die efficiency. Optimized for high bandwidth, the device uses static column circuitry and a 256K/spl times/4 organization to achieve data rates >180 Mb/s at worst-case voltage and temperature conditions. The 5.97-mm/spl times/11.4-mm die incorporates a flexible laser blown fuse link redundancy scheme which can repair a wide variety of fabrication defects. Typical row access and cycle times are 85 and 190 ns, respectively, achieving >21-Mb/s bandwidth in the non-optimized row access mode. Although some DC power is dissipated in static circuitry, active power consumption has been kept to 225 mW (45 mA), and standby power consumption has been reduced to 2.5 mW (0.5 mA).