任务敏感的多模式视频编码系统功耗控制方法

在嵌入式多模式视频编码系统中,动态电压频率调整(Dynamic Voltage and Frequency Scaling,DVFS)技术可在一定程序上节约系统能耗,然而持续降低电压和频率可能影响处理器接口资源的传输性能,甚至导致系统无法正常工作.针对该问题,提出了一种任务敏感的功耗控制方法.通过研究多模式视频编码任务量和处理器资源之间的关系,建立一个任务敏感的资源配置模型,基于该模型设计了一个自适应功耗控制器,在系统工作过程中根据编码任务量的不同动态调节处理器工作频率和工作核数.实验表明,在满足多模式实时视频编码功能和性能要求的基础上,该文提出的方法与传统DVFS技术相比,单帧视频编码的平均功耗节省了11.4%.     

应用于超宽带系统中的低功耗、高速FFT/IFFT处理器设计

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器.采用8×8×2混合基算法进行FFT运算,实现了2路64点或者1路128点FFT功能,并为该算法提出了一种新型的8路并行反馈结构.该结构提高了处理器的数据吞吐率,降低了芯片功耗.为了减少处理器中的乘法数目,提高时序性能,提出了改进型移位加算法.设计的FFT/IFFT处理器采用SMIC 0.13μm CMOS工艺制造,芯片的核心面积为1.44mm2.测试结果表明,该芯片最高数据吞吐率到达1Gsample/s,在典型的工作频率500Msample/s下,芯片功耗为39.6mW.与现有同类型FFT芯片相比,该芯片面积缩小了40%,功耗减少了45%.     

基于高密度计算的多核处理器电力芯片低功耗设计系统

多核处理器电力芯片是目前多种系统的重要组成部分,设计低功耗电力芯片,能够更好地保证系统正常运行。目前设计的电力芯片低功耗系统运行速度较慢,功耗难以达到用户要求,为此该文应用高密度计算设计了一种多核处理器电力芯片低功耗系统。兼容系统多核处理器与层次化AHB总线,探索处理器电力芯片的整体结构,集中处理存储数据信息,不断调整系统算法参数,通过高密度分析引入矩阵进行数据解析,确保运行过程的安全性。在分析处理器调度性能的基础上,利用高密度处理对数据进行层次化处理,避免数据冗余造成的系统运行故障。实验结果表明,引入所设计系统后电力芯片功耗减少了60%,加速比达到3.992,可以有效提高电力芯片运行性能。     

英特尔发布至强5500系列处理器

本刊讯(记者杨海峰)3月31日,英特尔在京全球同步发布以英特尔至强5500系列处理器为首的17款企业级处理器。英特尔至强5500处理器与上一代处理器相比,性能提升了2倍以上,是英特尔15年来最重要的服务器芯片系列。据悉,基于至强5500芯片的服务器是单核服务器性能的9倍,闲置功耗比上一代产品降低了50%。     

一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计

Cache作为处理器和系统总线之间的桥梁,是芯片功耗的主要来源,低功耗Cache设计在嵌入式芯片设计中具有重要意义.传统Cache设计一般依赖于特定体系结构,难以在不同的系统中进行集成,通用性差.本文提出了一种低功耗高效率的AHB-AXI双总线结构联合Cache的IP设计.实验结果显示,本设计可以显著降低Cache功耗和提高系统性能.     

英特尔推动多核技术在嵌入式系统的应用

在过去相当长一段时间,处理器厂商都不遗余力地通过不断提高主频来提高处理器的性能.但是随着处理器的发展,单处理器核心内部晶体管的集成度已超过上亿个,主频提高带来的功耗及发热量呈几何倍数增长,传统处理器体系结构的瓶颈日益显现.于是,另一种全新的芯片构架诞生了,这就是多核处理器,即在单个芯片上集成多个个处理器内核.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

技术动态

德州仪器发布45纳米半导体制造工艺德州仪器(TI)发布了45纳米(nm)半导体制造工艺的细节,该工艺采用湿法光刻技术,可使每个硅片的芯片产出数量提高一倍,从而提高了工艺性能并降低了功耗。通过采用多种专有技术,TI将集成数百万晶体管的片上系统处理器的功能提升到新的水平,使性能提高30％,并同时降低 40％的功耗。     

基于DVS的动态电压转换器设计

针对低功耗技术中的DVS(Dynamic Voltage Scaling)电路,本文介绍了一种动态电压转换器的设计。PWM(Pulse Width Modulation)控制电路是DC／DC转换器中的关键部件,重点介绍了一种新型可控占空比数字PWM控制电路的结构和工作原理,分析了这种数字PWM发生器的工作过程。该电路功耗低,所占面积小,适用于在动态功耗管理电路中的集成。     

一种采用双环和自适应开关频率控制的恒压-恒流控制芯片的设计

本文设计了一款输出5V/2.0A的恒压(CV)-恒流(CC)控制芯片,采用flyback架构和源边反馈.该芯片采用双反馈环精确控制输出电压和输出电流,使得系统在工艺与温度等参数变化时具有更好的调整性能,优于通常使用的开环控制方法。同时系统可以根据输出电压值在恒压和恒流模式之间实现自动和平滑的切换,因而不会影响切换过程中的电压和电流调制精度,这很好地克服了使用迟滞比较器实现模式切换的数字控制方式的不足。通过采用有源电容倍增技术对电压反馈环实现片上补偿,可以不增加额外的封装管脚,并且有效地节省了芯片面积.为了在不牺牲瞬态响应性能的前提下减小芯片的无负载功耗,芯片应用了自适应开关频率控制模式,在轻载模式下,可自动降低开关频率以减小功耗.最低功耗可小于100mW .采用0.35-μm 40-V BCD工艺完成流片,芯片面积为1.5mm 1.0mm.由于线性调整度和负载调整度所造成的输出电压误差小于 1.7%.     

针对电压可调处理器的低功耗设计策略

在便携式系统的低功耗设计中，动态电源管理（Dynamic Power Management，DPM）和动态电压调节（Dynamic Voltage Scaling，DVS）已经成为比较通用的技术，并且很多实验数据表明DVS省电性能比DPM更为优越。本文针对电压可调的处理器，在理论证明的基础上提出了一种能够跟踪工作负载需求变化，在保证给定任务组中所有任务性能的同时实现系统能耗最优化的电压调节策略EOVSP（Energy Optimal Voltage Scaling Policy）。实验结果也表明，该策略在满足系统性能要求的前提下具有比一般DPM策略更好的省电性能。     

Elastic DVS Management in Processors With Discrete Voltage/Frequency Modes

Applying classical dynamic voltage scaling (DVS) techniques to real-time systems running on processors with discrete voltage/frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) versus energy consumption (which is a function of the processor speed). In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions. To make the proposed approach usable in real-world applications, the task model is enhanced to consider some of the real CPU characteristics, such as discrete voltage/frequency levels, switching overhead, task execution times nonlinear with the frequency, and tasks with different power consumption. Implementation issues and experimental results for the proposed algorithm are also discussed     

几种实时嵌入式系统DVS策略的分类比较

动态电压调节是一种有效的运用于实时嵌入式系统中的低功耗技术。实时嵌入式系统DVS技术不仅要实现系统功耗的降低,同时也要兼顾系统的实时性,满足任务的截止时间限。该文针对近几年实时嵌入式系统中DVS策略,首先介绍实时系统中DVS策略模型,对主流策略进行分类比较,并且对相应策略进行仿真,DVS策略可以取得10%～40%的能耗节省。     

操作系统级低功耗动态电压缩放算法分析

低功耗的设计已经成为嵌入式系统设计中一个非常重要的方面，而动态电压调度（Dynamic Voltage Scaling DVS）又被认为是降低功耗的一种有效手段。本文对各类针对系统的动态电压缩放算法做了较系统的总结，给出了算法的模型，重点描述了操作系统级的两类动态电压缩放算法——基于间隔和基于任务的动态电压调度算法，概述了针对编译级的任务内动态电压调度算法。文章对三类算法作了分析与比较，由此给出了结论与观点，对以后动态电压缩放算法的研究做了预测。     

Peak Power Minimizing Algorithm by Voltage Scheduling

For complicated electronic systems, to ensure high performance and reliability satisfaction, minimizing peak power consumption becomes one of the most important design goals. This paper addresses the problem of variable voltage scheduling on multlprocessor distributed systems, with the goal of shaping the power profile to minimizing peak power. A low peak power algorithm named LPPA is proposed to optimize power distribution via scaling voltage of the tasks on critical regions, based on the comprehensive analysis of how power consumption varies with latency. Compared with previous low peak power techniques, which simply scale voltage of tasks according to their timing critical degree, LPPA additionally take the power profile into count to further decrease the peak power. Experimental results show that the proposed voltage scheduling technique significantly improves the power characteristics over the existing power profile unaware scheduling technique. Meanwhile, energy consumption reduction is also obtained.     

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip (SoC). Dynamic voltage scaling (DVS) is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 m technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.     

一种便携通信设备节能算法

在便携通信设备中,如何在保证性能需求的基础上,有效提高能耗效率,延长电池供电时间是一个重要问题,在对现有节能算法进行研究的基础上,提出了一种用于便携通信设备微处理器的基于时隙的动态电压滑动算法（简称DVS算法）。仿真结果表明,该算法能够有效提高便携通信设备微处理器的能耗效率。     

Minimizing detection-to-boosting latency toward low-power error-resilient circuits

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.     

Leakage-Aware Multiprocessor Scheduling

When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46% for tight deadlines (1.5× the critical path length) and by up to 73% for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.

Dynamic Power Optimization Targeting User Delays in Interactive Systems

Power has become a major concern for mobile computing systems such as laptops and handhelds, on which a significant fraction of software usage is interactive instead of compute-intensive. For interactive systems, an analysis shows that more than 90 percent of system energy and time is spent waiting for user input. Such idle periods provide vast opportunities for dynamic power management (DPM) and voltage scaling (DVS) techniques to reduce system energy. In this work, we propose to utilize user interface information to predict user delays based on human-computer interaction history and theories from the field of psychology. We show that such a delay prediction can be combined with DPM/DVS for aggressive power optimization. We verify the effectiveness of our methodologies with usage traces collected on a personal digital assistant (PDA) and a system power model based on accurate measurements. Experiments show that using predicted user delays for DPM/DVS achieves an average of 21.9 percent system energy reduction with little sacrifice in user productivity or satisfaction