A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-$hbox{nV}surdhbox{Hz}$ input-referred noise density, a $-$8-dBV out-of-band third-order intermodulation intercept point, and a $+$ 15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.      

A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity

A high dynamic range CMOS image sensor providing a user-programmable power responsivity curve is presented. Each pixel integrates, besides a 4T active pixel structure, a voltage comparator and an analog memory to implement a time-to-saturation scheme while also providing the standard integrated photo-current signal. The sensor generates two 10-bit analog outputs allowing a typical dynamic range exceeding 120 dB with a temporal noise lower than 0.13% and a fixed pattern noise of 0.4% (1.7%) of the total signal swing (2 V) at low (high) irradiance without any external calibration procedures. A 140 times 140-pixel array has been fabricated in a 0.35-mum, two-poly four-metal (2P4M), 3.3-V standard CMOS technology. The chip measures 3.9 times 4.6 mm² with a pixel pitch of 15 mum and a fill factor of 20%.     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With 79-dB DR

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller V_ov(=V_GS-V_TH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 mum CMOS at 1.8-V supply. It achieves a 17.5-dBm IIP3 and a -40 dB HD3 for a 600-mV_{pp_diff} input signal amplitude. A 24-muV_rms noise gives a DR=79 dB, with 2.25-mA current consumption     

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current–voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-$muhbox{m}$ CMOS process, the transconductor occupies 220 $,times,$160 $muhbox{m}^{2}$ active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.      

Sub-1-V Supply Self-Adaptive CMOS Image Sensor Cell With 86-dB Dynamic Range

This letter presents a high dynamic range CMOS active pixel structure operating at a sub-1-V supply voltage, which is implemented using a standard 0.18-mum CMOS logic process. In order to improve the output voltage swing range and associated pixel dynamic range at a low supply voltage, a pMOS reset structure is incorporated into the pixel structure along with a photogate pixel structure based on the self-adaptive photosensing operation. At a low supply voltage of 0.9 V, the new pixel provides an output voltage swing range of 0.41 V and a high dynamic range of 86 dB, which is the highest among the reported pixel structures up to date operating at sub-1-V     

A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes

In this paper, the design, implementation and characterization of a continuous time transimpedance-based ASIC for the actuation and sensing of a high-Q MEMS tuning fork gyroscope (TFG) is presented. A T-network transimpedance amplifier (TIA) is used as the front-end for low-noise, sub-atto-Farad capacitive detection. The T-network TIA provides on-chip transimpedance gains of up to 25 MOmega, has a measured capacitive resolution of 0.02 aF/radicHz at 15 kHz, a wide dynamic range of 104 dB in a bandwidth of 10 Hz and consumes 400 muW of power. The CMOS interface ASIC uses this TIA as the front-end to sustain electromechanical oscillations in a MEMS TFG with motional impedance greater than 10 MOmega. The TFG interfaced with the ASIC yields a two-chip angular rate sensor with measured rate noise floor of 2.7deg/hr/radicHz, bias instability of 1deg/hr and rate sensitivity of 2 mV/deg/s. The IC is fabricated in a 0.6-mum standard CMOS process with an area of 2.25 mm² and consumes 15 mW.     

A 141-dB Dynamic Range CMOS Gas-Sensor Interface Circuit Without Calibration With 16-Bit Digital Output Word

In this paper, we present the design and the characterization of a wide-dynamic-range interface circuit for resistive gas-sensors able to operate without calibration. The circuit is based on resistance-to-frequency conversion, which guarantees low complexity. The state-of-the-art of this measurement method has been improved first by separating the resistance value controlled oscillator circuit (RCO) from the sensing device, thus leading to higher linearity performance, and then by exploiting a novel digital frequency measurement system. Measurement results on a silicon prototype, designed in a 0.35-mum CMOS technology, show that the circuit achieves, without calibration, a precision in resistance measurement of 0.4% over a range of 4 decades and better than 0.8% over 5 decades (dynamic range, DR = 141 dB). Furthermore, after calibration, it reaches a precision of 0.4% for resistance values ranging between 1 kOmega and 1 GOmega, thus leading to a DR of 168 dB. The prototype chip consumes less than 15 mW from a 3.3-V supply.     

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-μm CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain     

基于生物应用的低截止频率5阶Gm-C低通滤波器

设计了一款基于生物应用的截止频率为38.49 Hz的5阶跨导电容(Gm-C)低通滤波器.首先利用电流互抵技术设计实现了一款低Gm的运算跨导放大器(OTA),并基于此OTA,采用无源电感电容(LC)网络模拟法设计了一款5阶椭圆滤波器.最后基于华虹宏力0.35 μmCD350 60 V/80 V工艺应用Spectre仿真工具对滤波器进行仿真.结果表明,所设计的低通滤波器可以实现非常陡峭的过渡带,并在50 Hz工频信号处衰减达-43.812 dB;阻带衰减为-33.18 dB;通带内平均噪声为352.0 μV·Hz-1/2;总谐波失真为-56.24 dB;3.3 V电源电压下,5阶滤波器总功耗仅为11.73 μW.所设计的滤波器可以有效采集频率极低的生物信号并且滤除干扰信号.芯片面积为1 200 μm×728.μm.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

一种带宽可调的低通开关电容滤波器的设计

介绍了一种带宽可调的二阶低通开关电容滤波器，带宽调节范围为100～500Hz，调节精度约为100Hz。该滤波器用双层金属、双层多晶硅1．2μm的N阱MOS工艺实现，用于一个加速度传感器电路中。设计着重考虑了由时钟信号引起的、严重制约开关电路性能的各种因素，通过优化开关的时序，消除了电荷注入引起的非线性效应，并采用高电源电压抑制比的折叠结构运算放大器，以减轻电源噪声的影响，从而有效地改善了电路的精度。     

A 30-MHz low-jitter high-linearity CMOS voltage-controlled oscillator

A fully monolithic voltage-controlled oscillator (VCO) with an on-chip timing capacitor and a maximum oscillation frequency of 30 MHz is reported. Using a novel on-chip servo loop, the VCO displays less than 0.17% nonlinearity in its voltage-frequency transfer function from 1 to 15 MHz without trimming. An improved circuit topology that provides a large swing on the timing capacitor allows the VCO to obtain a cycle-to-cycle jitter of less than 100 p.p.m. The circuit operates on a 5-V supply with a die size of 104 mil/spl times/154 mil.     

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-$mu$ m CMOS

This paper presents a 100-kHz fifth-order Chebychev low-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequency tuning system based on the voltage-controlled-filter (VCF) architecture and voltage reference circuit, is fabricated in a 0.18-mum standard CMOS technology with a 0.5-V threshold voltage and consumes 443 muW from a power supply of 0.6 V. The output noise and the in-band IIP₃ are 575 pA_rms and 219 muA, respectively. The filter achieves a dynamic range of 89 dB.     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

一种新型椭圆低通滤波器的设计与实现

针对现有椭圆滤波器多采用查对曲线方法设计电路参数导致的滤波性能不佳,调试困难等问题[1],设计了一种新型椭圆低通滤波器.该滤波器采用高电位和地之间嫁接复电抗的方法设计电路,按照基于四端网络的分析方法获得滤波电路的传递函数.具有设计方法简单,调试方便,电路参数精确,电路稳定可靠,截止频率易于调节,并能获得较高的滤波技术指标的特点.实际应用结果表明,滤波器滤波效果较好,满足设计要求.     

A High Dynamic Range CMOS Image Sensor With Inpixel Light-to-Frequency Conversion

A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion has been designed. The prototype chip was fabricated in a standard 0.18-mum single-poly six-metal CMOS technology. The experimental results show that, operating at 1.2 V, the sensor can achieve a linear dynamic range of over 115 dB and an overall dynamic range of over 130 dB     

具有宽调谐范围的低电压对数域二阶低通滤波器

提出了一个由BiCMOS构成的对数域二阶低通滤波器,并采用跨导线性原理分析得到其传递函数。分析了晶体管的寄生电容对此滤波器频率特性的影响。PSpice仿真结果表明,该对数域低通二阶节的实际频率特性和理想特性基本一致。且具有宽频率调谐范围、低工作电压和低失真等特点,可用于对数域高阶滤波器的设计。