Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

Reliability issues for flip-chip packages

In this article, we review the reliability issues for plastic flip-chip packages, which have become an enabling technology for future packaging development. The evolution of area-array interconnects with high I/O counts and power dissipation has made thermal deformation an important reliability concern for flip-chip packages. Significant advances have been made in understanding the thermo-mechanical behavior of flip-chip packages based on recent studies using moiré interferometry. Results from moiré studies are reviewed by focusing on the role of the underfill to show how it reduces the shear strains of the solder balls but shifts the reliability concern to delamination of the underfill interfaces. The development of the high-resolution moiré interferometry based on the phase-shift technique provided a powerful method for quantitative analysis of thermal deformation and strain distribution for high-density flip-chip packages. This method has been applied to study plastic flip-chip packages and the results and impacts on delamination at the die/underfill interface and in the underfill region above the plated through-hole via are discussed. Here a related reliability problem of die cracking during packaging assembly and test is also discussed. Finally, we discuss briefly two emerging reliability issues for advanced flip-chip packages, one on the packaging effect on Cu/low k interconnect reliability and the other on electromigration of solder balls in flip-chip packages.     

Effects of solder reflow on the reliability of flip-chip on flex interconnections using anisotropic conductive adhesives

This work describes the work of an investigation of the effects of solder reflow process on the reliability of anisotropic conductive film (ACF) interconnection for flip-chip on flex (FCOF) applications. Experiments as well as computer modeling methods have been used. The results show that the contact resistance of ACF interconnections increases after the reflow and the magnitude of the increase is strongly correlated to the peak reflow temperature. In fact, nearly 40 percent of the joints are open when the peak reflow temperature is 260/spl deg/C, while there is no opening when the peak temperature is 210/spl deg/C. It is believed that the coefficient of thermal expansion (CTE) mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a three-dimensional (3-D) finite element (FE) model of an ACF joint has been analyzed in order to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process. The stress level at the interface between the particle and its surrounding materials is significant and it is the highest at the interface between the particle and the adhesive matrix.     

The Influence of Substrate Enhancement on Moisture Sensitivity Level (MSL) Performance for Green PBGA Packages

As the electronics industry migrates to the lead- and halogen-free (green) packages, many of the materials used in plastic ball-grid array (PBGA) substrates, in particular the molding compounds and die attaches, will have to be improved. The moisture sensitivity level (MSL) performance of the large nongreen PBGA packages are typically reduced by at least one JEDEC/IPC level at the lead-free reflow temperature of 260$^circ$C. Common failure mechanisms of traditional large size PBGA packages include popcorning, as well as delamination and cracks between the solder mask/copper interface in the multiple layer substrates. In this paper, the interfacial adhesion of traditional and advanced substrate materials and processing technologies are presented based on reliability tests of various PBGA packages subject to moisture soaking followed by reflow soldering at 260$^circ$C. It was found that substrate failures with delamination at the solder mask/copper interface were dramatically improved by introducing advanced materials and processes for multiple-layer substrates. However, the partial or full delamination at the mold compound/solder mask interface could still be observed after lead-free reflow soldering. There is an urgent need to improve the adhesion between mold compound/solder mask in order to achieve high MSL performance of large size and green PBGA packages.     

Investigation of the underfill delamination and cracking inflip-chip modules under temperature cyclic loading

In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

Hygrothermal Failures From Small Defects in Lead-Free Solder Reflowed Electronic Packages

Steam-driven delamination failure is a main failure mode in electronics packages during solder reflow. Steam pressures built up within interfaces in packages are sensitive functions of the reflow temperature. The switch to lead-free soldering will raise re-flow temperature by more than 20degC and double the equilibrium saturated steam pressure within defects in the package. The effects of saturated steam driven interfacial failure was analyzed using finite element in this study. Analyses revealed that packages which are thin and made using high thermal conductivity materials are at higher risk of failure than conventional packages made using standard materials. This suggests that electronics made with thick and inexpensive encapsulants are less prone to failure when switched to lead-free solder. Portable and mobile electronics which have low profiles and are made of high thermal conductive encapsulants are at higher risk when switched to lead-free solder reflow. Moreover, the study found that the critical temperature for failure is dependent on the defect size in the package. Reduction of initial defect size can reduce failures in high risk packages in lead-free solder reflow.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

ACF互联可靠性影响因素的研究进展

总结了材料、芯片结构和环境因素等对异向导电胶膜(Anisotropic Conductive Film;ACF)互联可靠性的影响。文献表明,ACF基体树脂的吸湿膨胀系数、粘结强度及玻璃转化温度严重影响组装产品的互联可靠性,而导电粒子的导电性、芯片的结构和焊盘的表面处理方式等对可靠性也有较大影响。文献中的可靠性试验表明,在上面提到的因素中,湿气是影响器件中ACF可靠性的主要因素。     

Evaluation of the Delamination in a Flip Chip Using Anisotropic Conductive Adhesive Films Under Moisture/Reflow Sensitivity Test

Anisotropic conductive adhesive films (ACFs) have been used for electronic assemblies such as the connection between a liquid crystal display panel and a flexible printed circuit board. ACF interconnection is expected to be a key technology for flip chip packaging, system-in-packaging, and chip size packaging. This paper presents a methodology for quantitative evaluation of the delamination in a flip chip interconnected by an ACF under moisture/reflow sensitivity tests. Moisture concentration after moisture absorption was obtained by the finite element method. Then, the vapor pressure in the flip chip during solder reflow process was estimated. Finally the delamination was predicted by comparing the stress intensity factor of an interface crack due to vapor pressure with the delamination toughness. It is found that the delamination is well predicted by the present methodology.     

Effects of Anisotropic Conductive Film Viscosity on ACF Fillet Formation and Chip-On-Board Packages

In this paper, the effects of anisotropic conductive film (ACF) viscosity on ACF fillet formation and, ultimately, on the pressure cooker test (PCT) reliability of ACF flip chip assemblies were investigated. The ACF viscosity was controlled by varying the molecular weight of the epoxy materials. It was found that the ACF viscosity increased as the increase of molecular weight of the epoxy materials. However, there was little variation of the thermomechanical properties among the evaluated ACFs with different viscosites. Also, the results showed that the ACFs have no differences in moisture absorption rate, die adhesion strength, and degree-of-cure. In scanning electron microscopy images, the lower ACF viscosity resulted in the smoother ACF fillet shape and the higher fillet height. From the results of PCT, the ACF flip chip assembly with the smoother fillet shape showed better reliability in terms of contact resistance changes. After 130 h of PCT, the flip chip assembly with lower ACF viscosity also showed a lesser degree of delamination at the ACF/chip interface.     

ENIG Corrosion Induced by Second-Phase Precipitation

Materials analysis of a flip-chip package lot with solder bump interconnect failures revealed a new mechanism for corrosion of electroless nickel immersion gold surface finish. Detailed scanning and transmission electron microscopy (SEM and TEM) in conjunction with focused ion beam microscopy and electron dispersion analysis of the unsoldered ball grid array substrate pads on packages that exhibited flip-chip solder bump interconnect failures revealed an unusual and subtle defect in the original Ni(P) layer, which was ultimately responsible for flip-chip joint failure. Detailed TEM analysis of the defect regions showed that they consisted of Ni(P) particles of slightly different composition than the bulk Ni(P) layer. Microstructure changes around these incorporated particles indicated that the second-phase particles were deposited from the plating bath during the Ni(P) growth stage. The second-phase particles provided additional surface area for nucleation and growth of Ni(P). Ultimately, a low-density boundary region in the growing Ni(P) layer formed where the particle-induced growth front and the planar Ni(P) film growth front intersected. This low-density interface eventually terminated at the surface of the Ni(P) layer. In addition the growth from the second-phase particle created localized surface topology that was different than that of the surrounding Ni(P) layer. The low-density interfaces as well as the surface topology led to enhanced corrosion of the Ni(P) layer when exposed to the immersion gold plating process. In some cases the corrosion was severe enough to create voids in the Ni(P) layer. The exposed, oxidized Ni(P) surfaces in and around these enhanced corrosion regions did not wet when exposed to solder. This led to degradation in the strength of the solder joint and subsequent solder interconnect failure.     

Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

Advances in Vapor Pressure Modeling for Electronic Packaging

Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders     

Effect of Conductive Particle Properties on the Reliability of Anisotropic Conductive Film for Chip-on-Glass Applications

This paper describes how the material properties of conductive particles in anisotropic conductive films (ACFs) affect the electrical conductivity and the reliability of ACF interconnections for chip-on-glass (COG) applications. For the conductive particles, Au/Ni-coated polymer particles with a 5-diameter were used. Two different types of conductive particles were characterized with respect to their mechanical and electrical properties, such as ball hardness, recovery behavior, and electrical resistance. In addition, two ACFs were fabricated in the form of a double-layered structure, in which the thickness of the ACF and a nonconductive film (NCF) layer were optimized to have as many conductive particles as possible on the bump after COG bonding. The electrical contact resistance of an ACF interconnection in a COG structure depends mainly on the electrical properties of conductive particles in the ACF. The electrical reliability of an ACF interconnection in a COG structure also depends more on the electrical properties than the mechanical properties of conductive particles under a high-temperature and humid condition. Conductive particles with a lower electrical resistance, higher mechanical hardness, and lower recovery rate show better reliability than conductive particles with a higher electrical resistance, lower mechanical hardness, and higher recovery rate. Cross-sectional scanning electron microscopic (SEM) pictures of a COG interconnection show the deformation of two different conductive particles after the reliability tests. The ACF interconnections in the edge or corner of a driver IC show less reliable joints due to high absorption of moisture.     

Reliability of a flip-chip package thermally loaded between −55°C and 125°C

Low-temperature reliability of flip-chip plastic ball-grid array packages is a concern for manufacturers. Packages that perform well when thermally cycled from 20 to 120°C fail at an unacceptable rate when the temperature is extended down to −55°C. Electron-beam moiré was used to study local deformations in a flip-chip package and the interactions among the various materials found within the package. The specimen was subjected to a total of ten complete thermal cycles from −55 to 125°C over several nonconsecutive days. Debonding initiated between the solderball and the solder mask where that interface meets the printed circuit board. Deformation was also induced within the solderball, becoming more pronounced with more thermal cycles. Out-of-plane strains appear to be the dominant mechanism for deformation at this location.     

Formulation and characterization of anisotropic conductive adhesive paste for microelectronics packaging applications

There has been a steadily increasing interest in using electrically conductive adhesives as interconnecting materials in electronics manufacturing. In this paper, several anisotropic conductive adhesive (ACA) pastes were formulated, which consist of diglycidyl ether of bisphenol F or diglycidyl ether of bisphenol A as polymer matrix, imidazoles as curing agents, and different sizes of silver (Ag) powders or gold (Au)-coated polymer spheres as conductive particles. The effects of ACA resin and different curing agents, as well as different conductive particles, on flexible substrate of the flip-chip joint were studied. The results show that the size and type of different conductive particles have very limited influence on an ACA flip-chip joint. The ACA resin as well as the curing agent can affect the reliability of the joint. The same results can be applied for the failure analysis of ACA flip-chip technology.